[PATCH v2 1/2] drm/i915/gvt: Refine non privilege register address calucation

[Zhenyu Wang]

On 2019.11.27 00:07:35 +0800, Gao, Fred wrote:
> The BitField of non privilege register address is only from bit 2 to 25.
> 
> v2: use REG_GENMASK instead. (Zhenyu)
> 
> Signed-off-by: Gao Fred <fred.gao at intel.com>

For two in this series.

Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>

Thanks!

> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 45a9124e53b6..f346bdd266ab 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -508,7 +508,7 @@ static inline bool in_whitelist(unsigned int reg)
>  static int force_nonpriv_write(struct intel_vgpu *vgpu,
>  	unsigned int offset, void *p_data, unsigned int bytes)
>  {
> -	u32 reg_nonpriv = *(u32 *)p_data;
> +	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
>  	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
>  	u32 ring_base;
>  	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> @@ -528,7 +528,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
>  			bytes);
>  	} else
>  		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
> -			vgpu->id, reg_nonpriv, offset);
> +			vgpu->id, *(u32 *)p_data, offset);
>  
>  	return 0;
>  }
> -- 
> 2.17.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
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