[PATCH v4 2/3] drm/i915/gvt: check ggtt entry modification status for guest ctxs
Yan Zhao
yan.y.zhao at intel.com
Wed Apr 15 07:55:54 UTC 2020
for guest context, if its ggtt entry is modified after last context
shadowing, it is deemed as not the same context as last shadowed one.
v4: move valid bit and definiton of lrca type to first patch. (Kevin Tian)
v3: no change
v2: rebased to 5.6.0-rc4+
Suggested-by: Zhenyu Wang <zhenyuw at linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao at intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2a4b23f8aa74..b1b6a51c006a 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2341,12 +2341,29 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
{
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
int ret;
+ struct intel_vgpu_submission *s = &vgpu->submission;
+ struct intel_engine_cs *engine;
+ int i;
if (bytes != 4 && bytes != 8)
return -EINVAL;
off -= info->gtt_start_offset;
ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
+
+ /* if ggtt of last submitted context is written,
+ * that context is probably got unpinned.
+ * Set last shadowed ctx to invalid.
+ */
+ for_each_engine(engine, vgpu->gvt->gt->i915, i) {
+ if (!s->last_ctx[i].valid)
+ continue;
+
+ if (atomic_read(&s->last_ctx[i].lrca) ==
+ off >> info->gtt_entry_size_shift) {
+ s->last_ctx[i].valid = false;
+ }
+ }
return ret;
}
--
2.17.1
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