[PATCH V3] drm/gvt/i915: Fix two CFL MMIO handling caused by regression.

[Colin Xu]

Please ignore this one with a wrong title. Re-sending..

On 2020-06-01 11:04, Colin Xu wrote:
> Fixes: 43226e6fe798 (drm/i915/gvt: replaced register address with name)
>
> D_CFL was incorrectly removed for:
> GAMT_CHKN_BIT_REG
> GEN9_CTX_PREEMPT_REG
>
> V2: Update commit message.
> V3: Rebase and split Fixes and mis-handled MMIO.
>
> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>   drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3e88e3b5c43a..d2839cc036c1 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3131,8 +3131,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>   	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>   		 NULL, NULL);
>   
> -	MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
> -	MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
> +	MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
> +	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
>   
>   	return 0;
>   }

-- 
Best Regards,
Colin Xu