[PATCH] drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest

[Zhenyu Wang]

On 2020.05.08 19:50:18 +0800, Zhenyu Wang wrote:
> On 2020.05.08 11:13:38 +0000, Zhang, Xiong Y wrote:
> > > -----Original Message-----
> > > From: intel-gvt-dev <intel-gvt-dev-bounces at lists.freedesktop.org> On Behalf
> > > Of Zhenyu Wang
> > > Sent: Wednesday, May 6, 2020 5:59 PM
> > > To: intel-gvt-dev at lists.freedesktop.org
> > > Subject: [PATCH] drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest
> > > 
> > > As i915 won't allocate extra PDP for current default PML4 table, so for 3-level
> > > ppgtt guest, we would hit kernel pointer access failure on extra PDP pointers.
> > > So this trys to bypass that now.
> > > It won't impact real shadow PPGTT setup, so guest context still works.
> > > 
> > > This is verified on 4.15 guest kernel with i915.enable_ppgtt=1 to force on old
> > > aliasing ppgtt behavior.
> > > 
> > > Fixes: 4f15665ccbba ("drm/i915: Add ppgtt to GVT GEM context")
> > > Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gvt/scheduler.c | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
> > > b/drivers/gpu/drm/i915/gvt/scheduler.c
> > > index 9c3558489d17..6ab1d95c1fae 100644
> > > --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> > > +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> > > @@ -420,7 +420,11 @@ static void set_context_ppgtt_from_shadow(struct
> > > intel_vgpu_workload *workload,
> > >  		for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
> > >  			struct i915_page_directory * const pd =
> > >  				i915_pd_entry(ppgtt->pd, i);
> > > -
> > > +			/* skip now as current i915 ppgtt alloc won't allocate
> > > +			   top level pdp for non 4-level table, won't impact
> > > +			   shadow ppgtt. */
> > > +			if (!pd)
> > > +				break;
> > [Zhang, Xiong Y]  does it  exist in older kernel only ?  current staging code allocate 4 pdp for non 4-level table.
> 
> But in all current case we'll only allocate for pml4 as it checks hw info.
> 
> > I915_context_ppgtt_root_restore()  have the same issue, it should be modified also.
> 
> yeah, missed that although not shown in my test..
>

Double checked that ppgtt_root_save/restore is not relevant here,
which is only for shadow ctx that always align with i915 setup e.g in pml4.
But in this case for 3-level guest, we tried to directly set pdp ptr which
is not allocated in host pml4 setup. So have to skip that and update shadow
ctx state for 3-level pdp still works ok.

> > >  			px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
> > >  		}
> > >  	}
> > > --
> > > 2.26.2
> > > 
> > > _______________________________________________
> > > intel-gvt-dev mailing list
> > > intel-gvt-dev at lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
> 
> -- 
> Open Source Technology Center, Intel ltd.
> 
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