[PATCH] drm/gvt/i915: Fix two missed and add one MMIO handling for CFL

[Zhenyu Wang]

On 2020.05.18 13:35:06 +0800, Colin Xu wrote:
> D_CFL was incorrectly removed.
> GAMT_CHKN_BIT_REG
> GEN9_CTX_PREEMPT_REG
> Fixes: 43226e6fe798 (drm/i915/gvt: replaced register address with name)
>
> Add _PLANE_SURF_3_B.

Please put Fixes tag apart from commit description, e.g one blank line.
Or if target for specific commit fix, should just split it.

> 
> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3e88e3b5c43a..f39a6b20bbaf 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3055,6 +3055,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>  	MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>  	MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> +	MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>  
>  	MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
>  	MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
> @@ -3131,8 +3132,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>  	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>  		 NULL, NULL);
>  
> -	MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
> -	MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
> +	MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
> +	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
>  
>  	return 0;
>  }
> -- 
> 2.26.2
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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