[PATCH] drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang

[Zhenyu Wang]

On 2020.10.12 12:52:31 +0800, Colin Xu wrote:
> If guest fills non-priv bb on ApolloLake/Broxton as Mesa i965 does in:
> 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pw-)
> Due to the missing flush of bb filled by VM vCPU, host GPU hangs on
> executing these MI_BATCH_BUFFER.
> 
> Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
> PML4 PTE: PAT(0) PCD(1) PWT(1).
> 
> The performance is still expected to be low, will need further improvement.
>

Let's mitigate the hang issue now.

Acked-by: Zhenyu Wang <zhenyuw at linux.intel.com>

> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 32 ++++++++++++++++++++++++++++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 9891501da064..75cb0394c661 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1651,6 +1651,34 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
>  	return 0;
>  }
>  
> +/**
> + * FixMe:
> + * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
> + * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
> + * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
> + * these MI_BATCH_BUFFER.
> + * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
> + * PML4 PTE: PAT(0) PCD(1) PWT(1).
> + * The performance is still expected to be low, will need further improvement.
> + */
> +static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
> +			      void *p_data, unsigned int bytes)
> +{
> +	u64 pat =
> +		GEN8_PPAT(0, CHV_PPAT_SNOOP) |
> +		GEN8_PPAT(1, 0) |
> +		GEN8_PPAT(2, 0) |
> +		GEN8_PPAT(3, CHV_PPAT_SNOOP) |
> +		GEN8_PPAT(4, CHV_PPAT_SNOOP) |
> +		GEN8_PPAT(5, CHV_PPAT_SNOOP) |
> +		GEN8_PPAT(6, CHV_PPAT_SNOOP) |
> +		GEN8_PPAT(7, CHV_PPAT_SNOOP);
> +
> +	vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
> +
> +	return 0;
> +}
> +
>  static int guc_status_read(struct intel_vgpu *vgpu,
>  			   unsigned int offset, void *p_data,
>  			   unsigned int bytes)
> @@ -2813,7 +2841,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>  
> -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
> +	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>  	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>  
>  	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> @@ -3323,6 +3351,8 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>  
> +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> +
>  	return 0;
>  }
>  
> -- 
> 2.28.0
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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