[PATCH] drm/i915/gvt: Add F_CMD_ACCESS for some GEN9 SKU WA MMIO access
Zhenyu Wang
zhenyuw at linux.intel.com
Tue Sep 8 09:13:15 UTC 2020
On 2020.09.08 15:25:33 +0800, Colin Xu wrote:
> Pin for review.
>
Looks good to me.
Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> On 2020-08-19 09:08, Colin Xu wrote:
> > Without F_CMD_ACCESS, guest LRI cmd will fail due to "access to
> > non-render register" when init below WAs:
> > WaDisableDynamicCreditSharing: GAMT_CHKN_BIT_REG
> > WaCompressedResourceSamplerPbeMediaNewHashMode: MMCD_MISC_CTRL
> >
> > So add F_CMD_ACCESS to the two MMIO.
> >
> > Signed-off-by: Colin Xu <colin.xu at intel.com>
> > ---
> > drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > index d55cb43c9bd4..840572add2d4 100644
> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > @@ -2922,7 +2922,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> > MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> > MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> > MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> > - MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
> > + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> > MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> > MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> > MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> > @@ -3138,7 +3138,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> > MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> > NULL, NULL);
> > - MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
> > + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> > MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
> > return 0;
>
> --
> Best Regards,
> Colin Xu
>
> _______________________________________________
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> intel-gvt-dev at lists.freedesktop.org
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