[PATCH V3] drm/i915/gvt: Allow zero out HWSP addr on hws_pga_write

[Zhenyu Wang]

On 2020.09.11 14:52:39 +0800, Colin Xu wrote:
> Guest driver may reset HWSP to 0 as init value during D3->D0:
> The full sequence is:
>  - Boot ->D0
>  - Update HWSP
>  - D0->D3
>  - ...In D3 state...
>  - D3->D0
>  - DMLR reset.
>  - Set engine HWSP to 0.
>  - Set engine ring mode to 0.
>  - Set engine HWSP to correct value.
>  - Set engine ring mode to correct value.
> Ring mode is masked register so set 0 won't take effect.
> However HWPS addr 0 is considered as invalid GGTT address which will
> report error like:
> gvt: vgpu 1: write invalid HWSP address, reg:0x2080, value:0x0
> gvt: vgpu 1: fail to emulate MMIO write 00002080 len 4
> Detected your guest driver doesn't support GVT-g.
> Now vgpu 2 will enter failsafe mode.
> 
> Zero out HWSP addr is considered as a valid setting from device driver
> so don't treat it as invalid HWSP addr.
> 
> V2:
> Treat HWSP addr 0 as valid. (zhenyu)
> 
> V3:
> Change patch title.
> 
> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3be37e6fe33d..809429a35ec2 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1489,7 +1489,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	const struct intel_engine_cs *engine =
>  		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
>  
> -	if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
> +	if (value != 0 &&
> +	    !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
>  		gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
>  			      offset, value);
>  		return -EINVAL;
> -- 

Good to me. Thanks!

Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>

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