[Intel-xe] [PATCH 06/21] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

Remove hsw_ips.c ifdefs

With IPS conditional build, this is not needed.

Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 4 +---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +-------
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8e92091c4a1b..5ab20ca7c000 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,7 @@
 
 #include <linux/time.h>
 
+#include "hsw_ips.h"
 #include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
@@ -37,7 +38,6 @@
 #include "intel_psr.h"
 
 #ifdef I915
-#include "hsw_ips.h"
 #include "vlv_sideband.h"
 #endif
 
@@ -2415,11 +2415,9 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
 
-#ifdef I915
 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
 	if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
 		min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
-#endif
 
 	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
 	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2d59330ff5ab..9c80292e5666 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -57,7 +57,6 @@
 
 #include "g4x_dp.h"
 #include "g4x_hdmi.h"
-#include "hsw_ips.h"
 #include "i9xx_plane.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_pll.h"
@@ -65,6 +64,7 @@
 #include "vlv_sideband.h"
 #endif
 
+#include "hsw_ips.h"
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_utils.h"
@@ -4039,9 +4039,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 			ilk_get_pfit_config(pipe_config);
 	}
 
-#ifdef I915
 	hsw_ips_get_config(pipe_config);
-#endif
 
 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
@@ -4725,7 +4723,6 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
 	else
 		crtc_state->linetime = hsw_linetime_wm(crtc_state);
 
-#ifdef I915
 	if (!hsw_crtc_supports_ips(crtc))
 		return 0;
 
@@ -4735,7 +4732,6 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
 
 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
 						       cdclk_state);
-#endif
 
 	return 0;
 }
@@ -4804,13 +4800,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 			return ret;
 	}
 
-#ifdef I915
 	if (HAS_IPS(dev_priv)) {
 		ret = hsw_ips_compute_config(state, crtc);
 		if (ret)
 			return ret;
 	}
-#endif
 
 	if (DISPLAY_VER(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
-- 
2.39.2