[Intel-xe] [PATCH 1/6] drm/xe: Start splitting xe_device_desc into graphics/media structures
Lucas De Marchi
lucas.demarchi at intel.com
Wed Apr 5 22:04:23 UTC 2023
On Mon, Apr 03, 2023 at 01:16:57PM -0700, Matt Roper wrote:
>Rather than storing all characteristics for an entire platform in the
>xe_device_desc structure, create secondary graphics and media structures
>to hold traits and feature flags specific to those IPs. This will
>eventually allow us to assign the graphics and media characteristics at
>runtime based on the contents of the relevant GMD_ID registers.
>
>For now, just move the IP versions into the new structures to keep
>things simple. Other IP-specific fields will migrate to these
>structures in future patches.
>
>Note that there's one functional change introduced by this: previously
>PVC was recognized as media version 12.60. That's technically true, but
>in practice the media engines are fused off on all production hardware.
>By simply not assigning a media IP structure to PVC it will effectively
>be treated as IP version 0.0 now (which the rest of the driver should
>treat as non-existent media).
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c | 103 ++++++++++++++++++++++++++----------
> 1 file changed, 74 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 91fed9d3105e..bfc2c61fdb99 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -42,11 +42,19 @@ struct xe_gt_desc {
> u32 mmio_adj_offset;
> };
>
>+struct xe_graphics_desc {
>+ u8 ver;
>+ u8 rel;
>+};
>+
>+struct xe_media_desc {
>+ u8 ver;
>+ u8 rel;
>+};
>+
> struct xe_device_desc {
>- u8 graphics_ver;
>- u8 graphics_rel;
>- u8 media_ver;
>- u8 media_rel;
>+ const struct xe_graphics_desc *graphics;
>+ const struct xe_media_desc *media;
>
> u64 platform_engine_mask; /* Engines supported by the HW */
>
>@@ -84,17 +92,57 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>
> #define NOP(x) x
>
>+static const struct xe_graphics_desc graphics_xelp = {
>+ .ver = 12,
>+ .rel = 0,
>+};
>+
>+static const struct xe_graphics_desc graphics_xelpp = {
>+ .ver = 12,
>+ .rel = 10,
>+};
>+
>+static const struct xe_graphics_desc graphics_xehpg = {
>+ .ver = 12,
>+ .rel = 55,
>+};
>+
>+static const struct xe_graphics_desc graphics_xehpc = {
>+ .ver = 12,
>+ .rel = 60,
>+};
>+
>+static const struct xe_graphics_desc graphics_xelpg = {
>+ .ver = 12,
>+ .rel = 70,
>+};
>+
>+static const struct xe_media_desc media_xelp = {
>+ .ver = 12,
>+ .rel = 0,
>+};
>+
>+static const struct xe_media_desc media_xehpm = {
>+ .ver = 12,
>+ .rel = 55,
>+};
>+
>+static const struct xe_media_desc media_xelpmp = {
>+ .ver = 13,
>+ .rel = 0,
>+};
I'm thinking if this isn't overly verbose with one letter different on
each of them :(. Not very happy with the direction here, but it seems
to be correct
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
>+
> /* Keep in gen based order, and chronological order within a gen */
> #define GEN12_FEATURES \
> .require_force_probe = true, \
>- .graphics_ver = 12, \
>- .media_ver = 12, \
> .dma_mask_size = 39, \
> .max_tiles = 1, \
> .vm_max_level = 3, \
> .vram_flags = 0
>
> static const struct xe_device_desc tgl_desc = {
>+ .graphics = &graphics_xelp,
>+ .media = &media_xelp,
> GEN12_FEATURES,
> PLATFORM(XE_TIGERLAKE),
> .platform_engine_mask =
>@@ -104,6 +152,8 @@ static const struct xe_device_desc tgl_desc = {
> };
>
> static const struct xe_device_desc adl_s_desc = {
>+ .graphics = &graphics_xelp,
>+ .media = &media_xelp,
> GEN12_FEATURES,
> PLATFORM(XE_ALDERLAKE_S),
> .platform_engine_mask =
>@@ -115,6 +165,8 @@ static const struct xe_device_desc adl_s_desc = {
> static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
>
> static const struct xe_device_desc adl_p_desc = {
>+ .graphics = &graphics_xelp,
>+ .media = &media_xelp,
> GEN12_FEATURES,
> PLATFORM(XE_ALDERLAKE_P),
> .platform_engine_mask =
>@@ -131,9 +183,10 @@ static const struct xe_device_desc adl_p_desc = {
> .is_dgfx = 1
>
> static const struct xe_device_desc dg1_desc = {
>+ .graphics = &graphics_xelpp,
>+ .media = &media_xelp,
> GEN12_FEATURES,
> DGFX_FEATURES,
>- .graphics_rel = 10,
> PLATFORM(XE_DG1),
> .platform_engine_mask =
> BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
>@@ -143,26 +196,18 @@ static const struct xe_device_desc dg1_desc = {
>
> #define XE_HP_FEATURES \
> .require_force_probe = true, \
>- .graphics_ver = 12, \
>- .graphics_rel = 50, \
> .has_range_tlb_invalidation = true, \
> .has_flat_ccs = true, \
> .dma_mask_size = 46, \
> .max_tiles = 1, \
> .vm_max_level = 3
>
>-#define XE_HPM_FEATURES \
>- .media_ver = 12, \
>- .media_rel = 50
>-
> static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };
> static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 };
> static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
>
> #define DG2_FEATURES \
> DGFX_FEATURES, \
>- .graphics_rel = 55, \
>- .media_rel = 55, \
> PLATFORM(XE_DG2), \
> .subplatforms = (const struct xe_subplatform_desc[]) { \
> { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
>@@ -181,15 +226,17 @@ static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
> .has_4tile = 1
>
> static const struct xe_device_desc ats_m_desc = {
>+ .graphics = &graphics_xehpg,
>+ .media = &media_xehpm,
> XE_HP_FEATURES,
>- XE_HPM_FEATURES,
>
> DG2_FEATURES,
> };
>
> static const struct xe_device_desc dg2_desc = {
>+ .graphics = &graphics_xehpg,
>+ .media = &media_xehpm,
> XE_HP_FEATURES,
>- XE_HPM_FEATURES,
>
> DG2_FEATURES,
> };
>@@ -216,14 +263,12 @@ static const struct xe_gt_desc pvc_gts[] = {
> };
>
> static const struct xe_device_desc pvc_desc = {
>+ .graphics = &graphics_xehpc,
> XE_HP_FEATURES,
>- XE_HPM_FEATURES,
> DGFX_FEATURES,
> PLATFORM(XE_PVC),
> .extra_gts = pvc_gts,
>- .graphics_rel = 60,
> .has_flat_ccs = 0,
>- .media_rel = 60,
> .platform_engine_mask = PVC_ENGINES,
> .vram_flags = XE_VRAM_FLAGS_NEED64K,
> .dma_mask_size = 52,
>@@ -254,16 +299,15 @@ static const struct xe_gt_desc xelpmp_gts[] = {
>
> static const struct xe_device_desc mtl_desc = {
> /*
>- * Real graphics IP version will be obtained from hardware GMD_ID
>- * register. Value provided here is just for sanity checking.
>+ * FIXME: Real graphics/media IP will be mapped from hardware
>+ * GMD_ID register. Hardcoded assignments here will go away soon.
> */
>+ .graphics = &graphics_xelpg,
>+ .media = &media_xelpmp,
> .require_force_probe = true,
>- .graphics_ver = 12,
>- .graphics_rel = 70,
> .dma_mask_size = 46,
> .max_tiles = 2,
> .vm_max_level = 3,
>- .media_ver = 13,
> .has_range_tlb_invalidation = true,
> PLATFORM(XE_METEORLAKE),
> .extra_gts = xelpmp_gts,
>@@ -406,10 +450,11 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> if (IS_ERR(xe))
> return PTR_ERR(xe);
>
>- xe->info.graphics_verx100 = desc->graphics_ver * 100 +
>- desc->graphics_rel;
>- xe->info.media_verx100 = desc->media_ver * 100 +
>- desc->media_rel;
>+ xe->info.graphics_verx100 = desc->graphics->ver * 100 +
>+ desc->graphics->rel;
>+ if (desc->media)
>+ xe->info.media_verx100 = desc->media->ver * 100 +
>+ desc->media->rel;
> xe->info.is_dgfx = desc->is_dgfx;
> xe->info.platform = desc->platform;
> xe->info.dma_mask_size = desc->dma_mask_size;
>--
>2.39.2
>
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