[Intel-xe] [PATCH 3/6] drm/xe: Move most platform traits to graphics IP

[Lucas De Marchi]

On Mon, Apr 03, 2023 at 01:16:59PM -0700, Matt Roper wrote:
>Most of the traits currently in the device descriptor structures are
>either tied to the graphics IP or should be inferred from the graphics
>IP.  This becomes important on MTL and beyond where IP versions are
>supposed to be detected from the hardware's GMD_ID registers rather than
>mapped from PCI devid.
>
>Engine masks are left where they are for now; they'll be dealt with
>separately in a future patch.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c | 110 ++++++++++++++++++------------------
> 1 file changed, 56 insertions(+), 54 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index e9c92034765c..ba56f92c3c5f 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -45,6 +45,17 @@ struct xe_gt_desc {
> struct xe_graphics_desc {
> 	u8 ver;
> 	u8 rel;
>+
>+	u8 dma_mask_size;	/* available DMA address bits */
>+	u8 max_tiles;		/* defaults to 1 if unset */
>+	u8 vm_max_level;
>+	u8 vram_flags;
>+
>+	u8 has_asid:1;
>+	u8 has_flat_ccs:1;
>+	u8 has_link_copy_engine:1;
>+	u8 has_range_tlb_invalidation:1;
>+	u8 supports_usm:1;
> };
>
> struct xe_media_desc {
>@@ -63,24 +74,18 @@ struct xe_device_desc {
> 	const struct xe_subplatform_desc *subplatforms;
> 	const struct xe_gt_desc *extra_gts;
>
>-	u8 dma_mask_size; /* available DMA address bits */
>-
> 	u8 gt; /* GT number, 0 if undefined */
>
> #define DEFINE_FLAG(name) u8 name:1
> 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
>
>-	u8 vram_flags;
>-	u8 max_tiles;
>-	u8 vm_max_level;
>-
>-	bool supports_usm;
>-	bool has_flat_ccs;
>+	/*
>+	 * FIXME: Xe doesn't care about presence/lack of 4tile since we can
>+	 * already determine that from the graphics IP version.  This flag
>+	 * should eventually move entirely into the display code's own logic.
>+	 */

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:               if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:               else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)


also used in gem selftests. But indeed, otherwise seems it would be
better to have it in the display side.



Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>


Lucas De Marchi