[Intel-xe] [PATCH 1/2] drm/xe: Always write GEN12_RCU_MODE.GEN12_RCU_MODE_CCS_ENABLE for CCS engines

[Matthew Brost]

On Wed, Apr 05, 2023 at 04:42:30PM -0700, Matt Roper wrote:
> On Wed, Apr 05, 2023 at 04:34:02PM -0700, Matthew Brost wrote:
> > If CCS0 was fused we did not write this register thus CCS engine were
> > not enabled resulting in driver load failures.
> > 
> > Signed-off-by: Matthew Brost <matthew.brost at intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> 
> I'm not sure why only BIT(0) was being checked specifically.  It looks
> like that was added in b9d18a2338c2d1 ("drm/xe: fix compute on
> XEHP_SDV"), but there's no explanation there of what it was actually
> trying to fix.  XEHPSDV isn't something we care about anymore, but it
> might be worth doing a quick test on a DG2_G10 that has CCS0 just to
> make sure there isn't some other problem lurking (DG2-G11 will always
> have CCS0 fused off).
> 

The BIT(0) doesn't seem to make much sense, it certainly is harmless to
write this register on every CCS engine.

CI seems to have a G10 and is clean. Going to merge this now.

Matt

> 
> Matt
> 
> > ---
> >  drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index 63a4efd5edcc..4b56c35b988d 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -253,7 +253,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
> >  	u32 ccs_mask =
> >  		xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
> >  
> > -	if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask & BIT(0))
> > +	if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
> >  		xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg,
> >  				_MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
> >  
> > -- 
> > 2.34.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation