[Intel-xe] [PATCH 2/2] drm/xe: Drop coalescing of GGTT invalidations

Niranjana Vishwanathapura niranjana.vishwanathapura at intel.com
Thu Apr 6 03:42:36 UTC 2023


On Wed, Apr 05, 2023 at 04:34:03PM -0700, Matthew Brost wrote:
>Causing a bunch of hangs driver load and in user space. Benefit is
>rather small too, so just drop this for to stablize the stack.
>

Looks like this should instead be revert of following patches?

drm/xe: Coalesce GGTT invalidations
drm/xe: Pad GGTT mapping with an extra page pointing to scratch

Niranjana

>Signed-off-by: Matthew Brost <matthew.brost at intel.com>
>---
> drivers/gpu/drm/xe/xe_bo.c         |  1 -
> drivers/gpu/drm/xe/xe_bo_types.h   |  2 --
> drivers/gpu/drm/xe/xe_ggtt.c       | 25 +------------------------
> drivers/gpu/drm/xe/xe_ggtt_types.h |  2 --
> 4 files changed, 1 insertion(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
>index 5460e6fe3c1f..c7f175a149be 100644
>--- a/drivers/gpu/drm/xe/xe_bo.c
>+++ b/drivers/gpu/drm/xe/xe_bo.c
>@@ -975,7 +975,6 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
> 			return bo;
> 	}
>
>-	bo->requested_size = size;
> 	if (flags & (XE_BO_CREATE_VRAM_MASK | XE_BO_CREATE_STOLEN_BIT) &&
> 	    !(flags & XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT) &&
> 	    xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) {
>diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
>index db217500a970..6071611a2b29 100644
>--- a/drivers/gpu/drm/xe/xe_bo_types.h
>+++ b/drivers/gpu/drm/xe/xe_bo_types.h
>@@ -23,8 +23,6 @@ struct xe_vm;
> struct xe_bo {
> 	/** @ttm: TTM base buffer object */
> 	struct ttm_buffer_object ttm;
>-	/** @requested_size: Requested size of this buffer object */
>-	size_t requested_size;
> 	/** @size: Size of this buffer object after alignment adjusting */
> 	size_t size;
> 	/** @flags: flags for this buffer object */
>diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
>index a430d1568890..93f78aba2c8e 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt.c
>+++ b/drivers/gpu/drm/xe/xe_ggtt.c
>@@ -273,15 +273,7 @@ void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
> 		xe_ggtt_set_pte(ggtt, start + offset, pte);
> 	}
>
>-	if (bo->size == bo->requested_size) {
>-		pte = xe_ggtt_pte_encode(ggtt->scratch ?: bo, 0);
>-		xe_ggtt_set_pte(ggtt, start + bo->size, pte);
>-	}
>-
>-	if (ggtt->invalidate) {
>-		xe_ggtt_invalidate(ggtt->gt);
>-		ggtt->invalidate = false;
>-	}
>+	xe_ggtt_invalidate(ggtt->gt);
> }
>
> static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
>@@ -302,19 +294,6 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
> 	if (err)
> 		return err;
>
>-	/*
>-	 * We add an extra page when mapping a BO in the GGTT so we can coalesce
>-	 * GGTT invalidations. Without this extra page GGTT prefetches can leave
>-	 * entries in the TLB pointing to an invalidation GGTT entry when in
>-	 * fact we have programmed this GGTT entry to a valid entry. BO aligned
>-	 * to 64k already have padding so no need to add an extra page.
>-	 */
>-	if (bo->size == bo->requested_size) {
>-		size += SZ_4K;
>-		if (end != U64_MAX)
>-			end += SZ_4K;
>-	}
>-
> 	mutex_lock(&ggtt->lock);
> 	err = drm_mm_insert_node_in_range(&ggtt->mm, &bo->ggtt_node, size,
> 					  alignment, 0, start, end, 0);
>@@ -344,8 +323,6 @@ void xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node)
> 	drm_mm_remove_node(node);
> 	node->size = 0;
>
>-	ggtt->invalidate = true;
>-
> 	mutex_unlock(&ggtt->lock);
> }
>
>diff --git a/drivers/gpu/drm/xe/xe_ggtt_types.h b/drivers/gpu/drm/xe/xe_ggtt_types.h
>index 8198aa784654..ea70aaef4b31 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt_types.h
>+++ b/drivers/gpu/drm/xe/xe_ggtt_types.h
>@@ -26,8 +26,6 @@ struct xe_ggtt {
> 	u64 __iomem *gsm;
>
> 	struct drm_mm mm;
>-
>-	bool invalidate;
> };
>
> #endif
>-- 
>2.34.1
>


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