[Intel-xe] [PATCH v2 4/9] drm/xe: Move engine masks into IP descriptor structures
Matt Roper
matthew.d.roper at intel.com
Thu Apr 6 20:18:40 UTC 2023
Break the top-level platform_engine_mask field into separate
hw_engine_mask fields in the graphics and media structures. Since
hardware has more flexibility to mix-and-match IP versions going
forward, this allows each IP to list exactly which engines it provides;
the final per-GT engine list can then be constructured from those:
* On platforms without a standalone media GT (i.e., media IP versions
prior to 13), the primary GT's engine list is the union of the
graphics IP's engine list and the media IP's engine list.
* Otherwise, GT0's engine list is the graphics IP's engine list.
* For GT1 and beyond, the type of GT determines which IP's engine list
is used.
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 97 ++++++++++++++++++-------------------
1 file changed, 46 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 332d3d31836b..4338c66834a9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -37,7 +37,6 @@ struct xe_subplatform_desc {
struct xe_gt_desc {
enum xe_gt_type type;
u8 vram_id;
- u64 engine_mask;
u32 mmio_adj_limit;
u32 mmio_adj_offset;
};
@@ -51,6 +50,8 @@ struct xe_graphics_desc {
u8 vm_max_level;
u8 vram_flags;
+ u64 hw_engine_mask; /* hardware engines provided by graphics IP */
+
u8 has_asid:1;
u8 has_flat_ccs:1;
u8 has_link_copy_engine:1;
@@ -61,14 +62,14 @@ struct xe_graphics_desc {
struct xe_media_desc {
u8 ver;
u8 rel;
+
+ u64 hw_engine_mask; /* hardware engines provided by media IP */
};
struct xe_device_desc {
const struct xe_graphics_desc *graphics;
const struct xe_media_desc *media;
- u64 platform_engine_mask; /* Engines supported by the HW */
-
enum xe_platform platform;
const char *platform_name;
const struct xe_subplatform_desc *subplatforms;
@@ -101,6 +102,8 @@ static const struct xe_graphics_desc graphics_xelp = {
.ver = 12,
.rel = 0,
+ .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
+
.dma_mask_size = 39,
.vm_max_level = 3,
};
@@ -109,6 +112,8 @@ static const struct xe_graphics_desc graphics_xelpp = {
.ver = 12,
.rel = 10,
+ .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
+
.dma_mask_size = 39,
.vm_max_level = 3,
};
@@ -123,6 +128,11 @@ static const struct xe_graphics_desc graphics_xehpg = {
.ver = 12,
.rel = 55,
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
+ BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
+ BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
+
XE_HP_FEATURES,
.vram_flags = XE_VRAM_FLAGS_NEED64K,
};
@@ -131,6 +141,15 @@ static const struct xe_graphics_desc graphics_xehpc = {
.ver = 12,
.rel = 60,
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
+ BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
+ BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
+ BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
+ BIT(XE_HW_ENGINE_BCS8) |
+ BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
+ BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
+
XE_HP_FEATURES,
.dma_mask_size = 52,
.max_tiles = 2,
@@ -147,6 +166,10 @@ static const struct xe_graphics_desc graphics_xelpg = {
.ver = 12,
.rel = 70,
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
+ BIT(XE_HW_ENGINE_CCS0),
+
XE_HP_FEATURES,
.max_tiles = 2,
@@ -156,16 +179,28 @@ static const struct xe_graphics_desc graphics_xelpg = {
static const struct xe_media_desc media_xem = {
.ver = 12,
.rel = 0,
+
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |
+ BIT(XE_HW_ENGINE_VECS0),
};
static const struct xe_media_desc media_xehpm = {
.ver = 12,
.rel = 55,
+
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |
+ BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1),
};
static const struct xe_media_desc media_xelpmp = {
.ver = 13,
.rel = 0,
+
+ .hw_engine_mask =
+ BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |
+ BIT(XE_HW_ENGINE_VECS0), /* TODO: add GSC0 */
};
static const struct xe_device_desc tgl_desc = {
@@ -173,10 +208,6 @@ static const struct xe_device_desc tgl_desc = {
.media = &media_xem,
PLATFORM(XE_TIGERLAKE),
.require_force_probe = true,
- .platform_engine_mask =
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
- BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
- BIT(XE_HW_ENGINE_VCS2),
};
static const struct xe_device_desc adl_s_desc = {
@@ -184,10 +215,6 @@ static const struct xe_device_desc adl_s_desc = {
.media = &media_xem,
PLATFORM(XE_ALDERLAKE_S),
.require_force_probe = true,
- .platform_engine_mask =
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
- BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
- BIT(XE_HW_ENGINE_VCS2),
};
static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
@@ -197,10 +224,6 @@ static const struct xe_device_desc adl_p_desc = {
.media = &media_xem,
PLATFORM(XE_ALDERLAKE_P),
.require_force_probe = true,
- .platform_engine_mask =
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
- BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
- BIT(XE_HW_ENGINE_VCS2),
.subplatforms = (const struct xe_subplatform_desc[]) {
{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
{},
@@ -216,10 +239,6 @@ static const struct xe_device_desc dg1_desc = {
DGFX_FEATURES,
PLATFORM(XE_DG1),
.require_force_probe = true,
- .platform_engine_mask =
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
- BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
- BIT(XE_HW_ENGINE_VCS2),
};
static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };
@@ -235,12 +254,6 @@ static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
{ } \
}, \
- .platform_engine_mask = \
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | \
- BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1) | \
- BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | \
- BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | \
- BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), \
.has_4tile = 1
static const struct xe_device_desc ats_m_desc = {
@@ -259,22 +272,10 @@ static const struct xe_device_desc dg2_desc = {
DG2_FEATURES,
};
-#define PVC_ENGINES \
- BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | \
- BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | \
- BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | \
- BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | \
- BIT(XE_HW_ENGINE_BCS8) | \
- BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS1) | \
- BIT(XE_HW_ENGINE_VCS2) | \
- BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | \
- BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3)
-
static const struct xe_gt_desc pvc_gts[] = {
{
.type = XE_GT_TYPE_REMOTE,
.vram_id = 1,
- .engine_mask = PVC_ENGINES,
.mmio_adj_limit = 0,
.mmio_adj_offset = 0,
},
@@ -286,27 +287,17 @@ static const struct xe_device_desc pvc_desc = {
PLATFORM(XE_PVC),
.require_force_probe = true,
.extra_gts = pvc_gts,
- .platform_engine_mask = PVC_ENGINES,
};
-#define MTL_MEDIA_ENGINES \
- BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | \
- BIT(XE_HW_ENGINE_VECS0) /* TODO: GSC0 */
-
static const struct xe_gt_desc xelpmp_gts[] = {
{
.type = XE_GT_TYPE_MEDIA,
.vram_id = 0,
- .engine_mask = MTL_MEDIA_ENGINES,
.mmio_adj_limit = 0x40000,
.mmio_adj_offset = 0x380000,
},
};
-#define MTL_MAIN_ENGINES \
- BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | \
- BIT(XE_HW_ENGINE_CCS0)
-
static const struct xe_device_desc mtl_desc = {
/*
* FIXME: Real graphics/media IP will be mapped from hardware
@@ -317,7 +308,6 @@ static const struct xe_device_desc mtl_desc = {
.require_force_probe = true,
PLATFORM(XE_METEORLAKE),
.extra_gts = xelpmp_gts,
- .platform_engine_mask = MTL_MAIN_ENGINES,
};
#undef PLATFORM
@@ -449,14 +439,19 @@ static void xe_info_init(struct xe_device *xe,
if (id == 0) {
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.vram_id = id;
- gt->info.__engine_mask = desc->platform_engine_mask;
+
+ gt->info.__engine_mask = desc->graphics->hw_engine_mask;
+ if (MEDIA_VER(xe) < 13 && desc->media)
+ gt->info.__engine_mask |= desc->media->hw_engine_mask;
+
gt->mmio.adj_limit = 0;
gt->mmio.adj_offset = 0;
} else {
gt->info.type = desc->extra_gts[id - 1].type;
gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
- gt->info.__engine_mask =
- desc->extra_gts[id - 1].engine_mask;
+ gt->info.__engine_mask = (gt->info.type == XE_GT_TYPE_MEDIA) ?
+ desc->media->hw_engine_mask :
+ desc->graphics->hw_engine_mask;
gt->mmio.adj_limit =
desc->extra_gts[id - 1].mmio_adj_limit;
gt->mmio.adj_offset =
--
2.39.2
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