[Intel-xe] [PATCH 04/41] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

Remove g4x_dp.h and dpio ifdefs. No longer needed.

Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  9 +--------
 drivers/gpu/drm/i915/display/intel_pps.c     | 13 ++-----------
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 24c96f388d52..b577e58aec97 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -54,7 +54,6 @@
 #include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_object.h"
 
-#include "g4x_dp.h"
 #include "g4x_hdmi.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_pll.h"
@@ -62,6 +61,7 @@
 #include "vlv_sideband.h"
 #endif
 
+#include "g4x_dp.h"
 #include "hsw_ips.h"
 #include "i915_drv.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9bd8a8416c58..6900cfb93dc8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -43,8 +43,8 @@
 #include <drm/drm_edid.h>
 #include <drm/drm_probe_helper.h>
 
-#ifdef I915
 #include "g4x_dp.h"
+#ifdef I915
 #include "i915_debugfs.h"
 #endif
 #include "i915_drv.h"
@@ -2191,10 +2191,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (pipe_config->splitter.enable)
 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
 
-#ifdef I915
 	if (!HAS_DDI(dev_priv))
 		g4x_dp_set_clock(encoder, pipe_config);
-#endif
 
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
@@ -5264,8 +5262,6 @@ static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
 				      struct intel_connector *connector)
 {
 	enum pipe pipe = INVALID_PIPE;
-
-#ifdef I915
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
@@ -5282,7 +5278,6 @@ static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
 		if (pipe != PIPE_A && pipe != PIPE_B)
 			pipe = PIPE_A;
 	}
-#endif
 
 	intel_backlight_setup(connector, pipe);
 }
@@ -5478,10 +5473,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 	intel_dp_set_default_sink_rates(intel_dp);
 	intel_dp_set_default_max_sink_lane_count(intel_dp);
 
-#ifdef I915
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
-#endif
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "Adding %s connector on [ENCODER:%d:%s]\n",
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 897a7b1beac1..6c39e311d53d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -3,6 +3,7 @@
  * Copyright © 2020 Intel Corporation
  */
 
+#include "g4x_dp.h"
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
@@ -10,17 +11,13 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpio_phy.h"
+#include "intel_dpio_phy.h"
 #include "intel_dpll.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
 #include "intel_pps.h"
 #include "intel_quirks.h"
 
-#ifdef I915
-#include "g4x_dp.h"
-#include "intel_dpio_phy.h"
-#endif
-
 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 				      enum pipe pipe);
 
@@ -86,7 +83,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
 	return 0;
 }
 
-#ifdef I915
 static void
 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 {
@@ -271,7 +267,6 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 
 	return pps_idx;
 }
-#endif
 
 typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
 
@@ -489,14 +484,12 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 
 	memset(regs, 0, sizeof(*regs));
 
-#ifdef I915
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else
 		pps_idx = intel_dp->pps.pps_idx;
-#endif
 
 	regs->pp_ctrl = PP_CONTROL(pps_idx);
 	regs->pp_stat = PP_STATUS(pps_idx);
@@ -1689,7 +1682,6 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		return;
 
 	if (HAS_PCH_SPLIT(dev_priv)) {
-#ifdef I915
 		u32 port_sel;
 
 		pp_reg = PP_CONTROL(0);
@@ -1716,7 +1708,6 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = PP_CONTROL(pipe);
 		panel_pipe = pipe;
-#endif
 	} else {
 		u32 port_sel;
 
-- 
2.39.2