[Intel-xe] [PATCH v2 0/8] Meteorlake interrupt & TLB handling updates
Matt Roper
matthew.d.roper at intel.com
Wed Apr 12 22:52:40 UTC 2023
Although Meteor Lake has multiple GTs, we need to be careful not to use
multi-tile flows when processing interrupts. The platform as a whole
only has a single copy of the SGunit interrupt registers, and interrupts
relating to the media GT are delivered as part of the primary GT's IRQ
reporting flow. Only when an engine (or GuC) interrupt is raised do we
need to determine which GT it relates to for further processing.
The whole multi-GT vs multi-tile situation is made more confusing by the
Xe driver's misuse of 'gt' as the target of all register operations.
That's probably something we should refactor in the future so that
xe_mmio_*() will take something more appropriate than an xe_gt
parameter.
With the fixes in this series, interrupts are now properly flowing on
both the primary and media GT for MTL. We're still seeing some TLB
invalidation timeouts, but those no longer seem to be caused by problems
with interrupt handling.
Matt Roper (8):
drm/xe/irq: Cleanup media GT interrupt flow
drm/xe/irq: Improve warnings and assertions for GT handling
drm/xe/irq: Process Gunit interrupts in relation to the device
drm/xe: Fix xe_mmio_rmw32 operation
drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt
mask
drm/xe: Include GT ID in error message if TLB invalidation times out
drm/xe: Invalidate TLB on all affected GTs during GGTT updates
drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations
drivers/gpu/drm/xe/xe_ggtt.c | 24 +++-
drivers/gpu/drm/xe/xe_ggtt_types.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 4 +
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 4 +-
drivers/gpu/drm/xe/xe_gt_types.h | 2 +
drivers/gpu/drm/xe/xe_guc.c | 11 +-
drivers/gpu/drm/xe/xe_irq.c | 115 +++++++++++++++-----
drivers/gpu/drm/xe/xe_mmio.h | 2 +-
8 files changed, 125 insertions(+), 39 deletions(-)
--
2.39.2
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