[Intel-xe] [PATCH v2 5/8] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask

[Lucas De Marchi]

On Wed, Apr 12, 2023 at 03:52:45PM -0700, Matt Roper wrote:
>Although primary and media GuC share a single interrupt enable bit, they
>each have distinct bits in the mask register.  Although we always enable
>interrupts for the primary GuC before the media GuC today (and never
>disable either of them), this might not always be the case in the
>future, so use a RMW when updating the mask register to ensure the other
>GuC's mask doesn't get clobbered.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi