[Intel-xe] [PATCH] drm/xe: Drop GFX_FLSH_CNTL_GEN6 write during GGTT invalidation

[Matt Roper]

The write of GFX_FLSH_CNTL_GEN6 was inherited from the i915 codebase
where it was used to force a flush of the write-combine buffer in cases
where the GSM/GGTT were mapped as WC.  Since Xe never uses WC mappings
of the GGTT, this register write is unnecessary.  Furthermore, this
register was removed on Xe_HP-based platforms, so this write winds up
clobbering an unrelated register.

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---

This write has also become unnecessary/unwanted in i915 for newer
platforms (gen9bc and earlier do use WC mappings and need this write,
but gen9lp and beyond do not).  Fei is working on that and should have
an i915 patch posted soon.

 drivers/gpu/drm/xe/xe_ggtt.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 0ae373b604f6..531c685cf2a1 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -196,11 +196,6 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
 {
 	/* TODO: vfunc for GuC vs. non-GuC */
 
-	/* TODO: i915 makes comments about this being uncached and
-	 * therefore flushing WC buffers.  Is that really true here?
-	 */
-	xe_mmio_write32(gt, GFX_FLSH_CNTL_GEN6.reg, GFX_FLSH_CNTL_EN);
-
 	if (gt->uc.guc.submission_state.enabled) {
 		int seqno;
 
-- 
2.39.2