[Intel-xe] [PATCH] drm/xe/sr: Apply masked registers properly

[Matt Atwood]

On Wed, Apr 19, 2023 at 03:49:09PM -0700, Matt Roper wrote:
> The 'clear' field for register save/restore entries was being placed in
> the value bits of the register rather than the mask bits; make sure it
> gets shifted into the mask bits.
> 
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Atwood <matthew.s.atwood at intel.com>
tested this, fixes the following behavior:
Before
[drm:xe_reg_sr_apply_mmio [xe]] REG[0x20ec] = 0x00000002
After
[drm:xe_reg_sr_apply_mmio [xe]] REG[0x20ec] = 0x00020002

Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_reg_sr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index feed87109e93..f77203b32026 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -150,7 +150,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
>  	 * supposed to set all bits.
>  	 */
>  	if (entry->masked_reg)
> -		val = (entry->clr_bits ?: entry->set_bits << 16);
> +		val = (entry->clr_bits ?: entry->set_bits) << 16;
>  	else if (entry->clr_bits + 1)
>  		val = (entry->reg_type == XE_RTP_REG_MCR ?
>  		       xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) :
> -- 
> 2.40.0
>