[Intel-xe] [PATCH v2] drm/xe: Fix xe_mmio_rmw32 operation

[Matt Roper]

xe_mmio_rmw32 was failing to invert the passed in mask, resulting in a
register update that wasn't the expected RMW operation.  Fortunately the
impact of this mistake was limited, since this function isn't heavily
used in Xe right now; this will mostly fix some GuC PM interrupt
unmasking.  The display code also had a wrapper that was using
xe_mmio_rmw32, but that wrapper was working around the misimplementation
by inverting the 'clear' mask passed; that wrapper can now go pack to
passing the 'clear' parameter properly.

v2:
 - Rename parameters as 'clr' and 'set' to clarify semantics.  (Lucas)
 - Undo xe_de.h's workaround for this misimplementation.  (Maarten)

Cc: Lucas De Marchi <lucas.demarchi at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Link: https://lore.kernel.org/r/20230412225248.3229571-5-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 drivers/gpu/drm/xe/display/xe_de.h | 2 +-
 drivers/gpu/drm/xe/xe_mmio.h       | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
index 9f92fdb4159a..000379f8702e 100644
--- a/drivers/gpu/drm/xe/display/xe_de.h
+++ b/drivers/gpu/drm/xe/display/xe_de.h
@@ -45,7 +45,7 @@ intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
 static inline u32
 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
 {
-	return xe_mmio_rmw32(to_gt(i915), reg.reg, ~clear, set);
+	return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
 }
 
 static inline int
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 388a633b438b..a36c52bc098b 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -34,13 +34,13 @@ static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg)
 	return readl(gt->mmio.regs + reg);
 }
 
-static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 mask,
-				 u32 val)
+static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
+				 u32 set)
 {
 	u32 old, reg_val;
 
 	old = xe_mmio_read32(gt, reg);
-	reg_val = (old & mask) | val;
+	reg_val = (old & ~clr) | set;
 	xe_mmio_write32(gt, reg, reg_val);
 
 	return old;
-- 
2.40.0