[Intel-xe] [PATCH v2 15/17] drm/xe: Annotate masked registers used by RTP

[Lucas De Marchi]

On Mon, Apr 24, 2023 at 01:49:24PM -0700, Matt Roper wrote:
>On Fri, Apr 21, 2023 at 03:32:56PM -0700, Lucas De Marchi wrote:
>> Go over all registers used in xe_rtp tables and mark the registers as
>> masked if they were passed a XE_RTP_ACTION_FLAG(MASKED_REG) flag.
>> This will allow the flag to be removed in future when xe_rtp starts
>> using the real xe_reg_t type.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 +-
>>  drivers/gpu/drm/xe/regs/xe_gt_regs.h     | 46 ++++++++++++------------
>>  2 files changed, 24 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> index c13aac8f900c..f8851e045c0a 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> @@ -21,7 +21,7 @@
>>  #define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -> pages */
>>  #define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -> pages */
>>
>> -#define RING_PSMI_CTL(base)			XE_REG((base) + 0x50)
>> +#define RING_PSMI_CTL(base)			XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
>>  #define   RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)
>>  #define   WAIT_FOR_EVENT_POWER_DOWN_DISABLE	REG_BIT(7)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 64ab2255a406..c6949cec1dc3 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -45,19 +45,19 @@
>>  #define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
>>  #define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
>>
>> -#define FF_SLICE_CS_CHICKEN1			XE_REG(0x20e0)
>> +#define FF_SLICE_CS_CHICKEN1			XE_REG(0x20e0, XE_REG_OPTION_MASKED)
>>  #define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)
>>
>> -#define FF_SLICE_CS_CHICKEN2			XE_REG(0x20e4)
>> +#define FF_SLICE_CS_CHICKEN2			XE_REG(0x20e4, XE_REG_OPTION_MASKED)
>>  #define   PERF_FIX_BALANCING_CFE_DISABLE	REG_BIT(15)
>>
>> -#define CS_DEBUG_MODE1				XE_REG(0x20ec)
>> +#define CS_DEBUG_MODE1				XE_REG(0x20ec, XE_REG_OPTION_MASKED)
>>  #define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)
>>  #define   REPLAY_MODE_GRANULARITY		REG_BIT(0)
>>
>>  #define PS_INVOCATION_COUNT			XE_REG(0x2348)
>>
>> -#define CS_CHICKEN1				XE_REG(0x2580)
>> +#define CS_CHICKEN1				XE_REG(0x2580, XE_REG_OPTION_MASKED)
>>  #define   PREEMPT_GPGPU_LEVEL(hi, lo)		(((hi) << 2) | ((lo) << 1))
>>  #define   PREEMPT_GPGPU_MID_THREAD_LEVEL	PREEMPT_GPGPU_LEVEL(0, 0)
>>  #define   PREEMPT_GPGPU_THREAD_GROUP_LEVEL	PREEMPT_GPGPU_LEVEL(0, 1)
>> @@ -77,10 +77,10 @@
>>  #define XEHP_TILE0_ADDR_RANGE			XE_REG_MCR(0x4900)
>>  #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
>>
>> -#define CHICKEN_RASTER_1			XE_REG_MCR(0x6204)
>> +#define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
>>  #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>>
>> -#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208)
>> +#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
>>  #define   TBIMR_FAST_CLIP			REG_BIT(5)
>>
>>  #define VFLSKPD					XE_REG_MCR(0x62a8)
>
>This one should be masked as well (bspec 46114).

indeed, this one as using the different syntax for MASKED_REG
so it went missing on the this conversion.

>
>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

thanks
Lucas De Marchi