[Intel-xe] [PATCH 2/4] drm/xe/ras: Log the GT hw errors.
Iddamsetty, Aravind
aravind.iddamsetty at intel.com
Tue Apr 25 04:26:20 UTC 2023
On 06-04-2023 14:56, Himal Prasad Ghimiray wrote:
> From: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
>
> Count the CORRECTABLE and FATAL GT hardware errors as
> signaled by relevant interrupt and respective registers.
>
> For non relevant interrupts count them as driver interrupt error.
>
> For platform supporting error vector registers count and report
> the respective vector errors.
>
> Co-authored-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 77 ++++++-
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_gt.c | 29 +++
> drivers/gpu/drm/xe/xe_gt_types.h | 43 ++++
> drivers/gpu/drm/xe/xe_irq.c | 332 ++++++++++++++++++++++++---
> drivers/gpu/drm/xe/xe_pci.c | 3 +
> 6 files changed, 453 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index dff74b093d4e..b3d35d0c5a77 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -122,14 +122,50 @@ enum hardware_error {
> HARDWARE_ERROR_MAX,
> };
>
> +#define DEV_PCIEERR_STATUS _MMIO(0x100180)
> +#define DEV_PCIEERR_IS_FATAL(x) (REG_BIT(2) << (x * 4))
> #define _DEV_ERR_STAT_FATAL 0x100174
> #define _DEV_ERR_STAT_NONFATAL 0x100178
> #define _DEV_ERR_STAT_CORRECTABLE 0x10017c
> #define DEV_ERR_STAT_REG(x) _MMIO(_PICK_EVEN((x), \
> _DEV_ERR_STAT_CORRECTABLE, \
> _DEV_ERR_STAT_NONFATAL))
> +
> #define DEV_ERR_STAT_GT_ERROR REG_BIT(0)
>
> +enum gt_vctr_registers {
> + ERR_STAT_GT_VCTR0 = 0,
> + ERR_STAT_GT_VCTR1,
> + ERR_STAT_GT_VCTR2,
> + ERR_STAT_GT_VCTR3,
> + ERR_STAT_GT_VCTR4,
> + ERR_STAT_GT_VCTR5,
> + ERR_STAT_GT_VCTR6,
> + ERR_STAT_GT_VCTR7,
> +};
> +
> +#define ERR_STAT_GT_COR_VCTR_LEN (4)
> +#define _ERR_STAT_GT_COR_VCTR_0 0x1002a0
> +#define _ERR_STAT_GT_COR_VCTR_1 0x1002a4
> +#define _ERR_STAT_GT_COR_VCTR_2 0x1002a8
> +#define _ERR_STAT_GT_COR_VCTR_3 0x1002ac
> +#define ERR_STAT_GT_COR_VCTR_REG(x) _MMIO(_PICK_EVEN((x), \
> + _ERR_STAT_GT_COR_VCTR_0, \
> + _ERR_STAT_GT_COR_VCTR_1))
> +
> +#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
> +#define _ERR_STAT_GT_FATAL_VCTR_0 0x100260
> +#define _ERR_STAT_GT_FATAL_VCTR_1 0x100264
> +#define _ERR_STAT_GT_FATAL_VCTR_2 0x100268
> +#define _ERR_STAT_GT_FATAL_VCTR_3 0x10026c
> +#define _ERR_STAT_GT_FATAL_VCTR_4 0x100270
> +#define _ERR_STAT_GT_FATAL_VCTR_5 0x100274
> +#define _ERR_STAT_GT_FATAL_VCTR_6 0x100278
> +#define _ERR_STAT_GT_FATAL_VCTR_7 0x10027c
> +#define ERR_STAT_GT_FATAL_VCTR_REG(x) _MMIO(_PICK_EVEN((x), \
> + _ERR_STAT_GT_FATAL_VCTR_0, \
> + _ERR_STAT_GT_FATAL_VCTR_1))
> +
> #define _ERR_STAT_GT_COR 0x100160
> #define _ERR_STAT_GT_NONFATAL 0x100164
> #define _ERR_STAT_GT_FATAL 0x100168
> @@ -137,7 +173,42 @@ enum hardware_error {
> _ERR_STAT_GT_COR, \
> _ERR_STAT_GT_NONFATAL))
>
> -#define EU_GRF_ERROR REG_BIT(15)
> -#define EU_IC_ERROR REG_BIT(14)
> -
> +#define EU_GRF_COR_ERR (15)
> +#define EU_IC_COR_ERR (14)
> +#define SLM_COR_ERR (13)
> +#define SAMPLER_COR_ERR (12)
> +#define GUC_COR_ERR (1)
> +#define L3_SNG_COR_ERR (0)
> +
> +#define PVC_COR_ERR_MASK \
> + (REG_BIT(GUC_COR_ERR) | \
> + REG_BIT(SLM_COR_ERR) | \
> + REG_BIT(EU_IC_COR_ERR) | \
> + REG_BIT(EU_GRF_COR_ERR))
> +
> +#define EU_GRF_FAT_ERR (15)
> +#define EU_IC_FAT_ERR (14)
> +#define SLM_FAT_ERR (13)
> +#define SAMPLER_FAT_ERR (12)
> +#define SQIDI_FAT_ERR (9)
> +#define IDI_PAR_FAT_ERR (8)
> +#define GUC_FAT_ERR (6)
> +#define L3_ECC_CHK_FAT_ERR (5)
> +#define L3_DOUBLE_FAT_ERR (4)
> +#define FPU_UNCORR_FAT_ERR (3)
> +#define ARRAY_BIST_FAT_ERR (1)
> +
> +#define PVC_FAT_ERR_MASK \
> + (REG_BIT(FPU_UNCORR_FAT_ERR) | \
> + REG_BIT(GUC_FAT_ERR) | \
> + REG_BIT(SLM_FAT_ERR) | \
> + REG_BIT(EU_GRF_FAT_ERR))
> +
> +#define GT_HW_ERROR_MAX_ERR_BITS 16
> +
> +#define _SLM_ECC_ERROR_CNT 0xe7f4
> +#define _SLM_UNCORR_ECC_ERROR_CNT 0xe7c0
> +#define SLM_ECC_ERROR_CNTR(x) _MMIO((x) == HARDWARE_ERROR_CORRECTABLE ? \
> + _SLM_ECC_ERROR_CNT : \
> + _SLM_UNCORR_ECC_ERROR_CNT)
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 88f863edc41c..ecabf4d6690d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -99,6 +99,8 @@ struct xe_device {
> bool has_link_copy_engine;
> /** @enable_display: display enabled */
> bool enable_display;
> + /** @has_gt_error_vectors: whether platform supports ERROR VECTORS */
> + bool has_gt_error_vectors;
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> struct xe_device_display_info {
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index bc821f431c45..ce9ce2748394 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -44,6 +44,35 @@
> #include "xe_wa.h"
> #include "xe_wopcm.h"
>
> +static const char * const xe_gt_driver_errors_to_str[] = {
> + [INTEL_GT_DRIVER_ERROR_INTERRUPT] = "INTERRUPT",
> +};
> +
> +void xe_gt_log_driver_error(struct xe_gt *gt,
> + const enum xe_gt_driver_errors error,
> + const char *fmt, ...)
> +{
> + struct va_format vaf;
> + va_list args;
> +
> + va_start(args, fmt);
> + vaf.fmt = fmt;
> + vaf.va = &args;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(xe_gt_driver_errors_to_str) !=
> + INTEL_GT_DRIVER_ERROR_COUNT);
> +
> + WARN_ON_ONCE(error >= INTEL_GT_DRIVER_ERROR_COUNT);
> +
> + gt->errors.driver[error]++;
> +
> + drm_err_ratelimited(>_to_xe(gt)->drm, "GT%u [%s] %pV",
> + gt->info.id,
> + xe_gt_driver_errors_to_str[error],
> + &vaf);
> + va_end(args);
> +}
> +
> struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
> {
> struct xe_gt *search;
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index 8f29aba455e0..9580a40c0142 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -33,6 +33,43 @@ enum xe_gt_type {
> typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
> typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)];
>
> +/* Count of GT Correctable and FATAL HW ERRORS */
> +enum intel_gt_hw_errors {
> + INTEL_GT_HW_ERROR_COR_SUBSLICE = 0,
> + INTEL_GT_HW_ERROR_COR_L3BANK,
> + INTEL_GT_HW_ERROR_COR_L3_SNG,
> + INTEL_GT_HW_ERROR_COR_GUC,
> + INTEL_GT_HW_ERROR_COR_SAMPLER,
> + INTEL_GT_HW_ERROR_COR_SLM,
> + INTEL_GT_HW_ERROR_COR_EU_IC,
> + INTEL_GT_HW_ERROR_COR_EU_GRF,
> + INTEL_GT_HW_ERROR_FAT_SUBSLICE,
> + INTEL_GT_HW_ERROR_FAT_L3BANK,
> + INTEL_GT_HW_ERROR_FAT_ARR_BIST,
> + INTEL_GT_HW_ERROR_FAT_FPU,
> + INTEL_GT_HW_ERROR_FAT_L3_DOUB,
> + INTEL_GT_HW_ERROR_FAT_L3_ECC_CHK,
> + INTEL_GT_HW_ERROR_FAT_GUC,
> + INTEL_GT_HW_ERROR_FAT_IDI_PAR,
> + INTEL_GT_HW_ERROR_FAT_SQIDI,
> + INTEL_GT_HW_ERROR_FAT_SAMPLER,
> + INTEL_GT_HW_ERROR_FAT_SLM,
> + INTEL_GT_HW_ERROR_FAT_EU_IC,
> + INTEL_GT_HW_ERROR_FAT_EU_GRF,
> + INTEL_GT_HW_ERROR_FAT_TLB,
> + INTEL_GT_HW_ERROR_FAT_L3_FABRIC,
> + INTEL_GT_HW_ERROR_COUNT
> +};
> +
> +enum xe_gt_driver_errors {
> + INTEL_GT_DRIVER_ERROR_INTERRUPT = 0,
> + INTEL_GT_DRIVER_ERROR_COUNT
> +};
Let's have driver errors as a separate patch and limit this to only HW
errors.
Thanks,
Aravind.
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