[Intel-xe] [PATCH 02/15] drm/xe/xe2: Add GT topology readout

[Matt Atwood]

On Fri, Aug 11, 2023 at 09:06:05AM -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper at intel.com>
> 
> Xe2 platforms have three DSS fuse registers for both geometry and
> compute.
> 
Bspec: 67171, 67537, 67401, 67536

> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
>  drivers/gpu/drm/xe/xe_gt_topology.c  | 16 +++++++++++-----
>  drivers/gpu/drm/xe/xe_gt_types.h     |  2 +-
>  3 files changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index c93d8f8cd93a5..ad7ae6a28caca 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -164,6 +164,9 @@
>  #define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
>  #define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
>  #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
> +#define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
> +#define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
> +#define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
>  
>  #define GDRST					XE_REG(0x941c)
>  #define   GRDOM_GUC				REG_BIT(3)
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index d4bbd0a835c22..a8d7f272c30a0 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -65,7 +65,10 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
>  static void
>  get_num_dss_regs(struct xe_device *xe, int *geometry_regs, int *compute_regs)
>  {
> -	if (GRAPHICS_VERx100(xe) == 1260) {
> +	if (GRAPHICS_VER(xe) > 20) {
> +		*geometry_regs = 3;
> +		*compute_regs = 3;
> +	} else if (GRAPHICS_VERx100(xe) == 1260) {
>  		*geometry_regs = 0;
>  		*compute_regs = 2;
>  	} else if (GRAPHICS_VERx100(xe) >= 1250) {
> @@ -90,15 +93,18 @@ xe_gt_topology_init(struct xe_gt *gt)
>  	 * Register counts returned shouldn't exceed the number of registers
>  	 * passed as parameters below.
>  	 */
> -	drm_WARN_ON(&xe->drm, num_geometry_regs > 1);
> -	drm_WARN_ON(&xe->drm, num_compute_regs > 2);
> +	drm_WARN_ON(&xe->drm, num_geometry_regs > 3);
> +	drm_WARN_ON(&xe->drm, num_compute_regs > 3);
>  
>  	load_dss_mask(gt, gt->fuse_topo.g_dss_mask,
>  		      num_geometry_regs,
> -		      XELP_GT_GEOMETRY_DSS_ENABLE);
> +		      XELP_GT_GEOMETRY_DSS_ENABLE,
> +		      XE2_GT_GEOMETRY_DSS_1,
> +		      XE2_GT_GEOMETRY_DSS_2);
>  	load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
>  		      XEHP_GT_COMPUTE_DSS_ENABLE,
> -		      XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
> +		      XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,
> +		      XE2_GT_COMPUTE_DSS_2);
>  	load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
>  
>  	xe_gt_topology_dump(gt, &p);
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index 35b8c19fa8bf5..48fd698ff62aa 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -24,7 +24,7 @@ enum xe_gt_type {
>  	XE_GT_TYPE_MEDIA,
>  };
>  
> -#define XE_MAX_DSS_FUSE_REGS	2
> +#define XE_MAX_DSS_FUSE_REGS	3
>  #define XE_MAX_EU_FUSE_REGS	1
>  
>  typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
> -- 
> 2.40.1
>