[Intel-xe] [PATCH 3/6] drm/xe: add GSCCS irq support

[Matt Roper]

On Wed, Aug 16, 2023 at 11:04:22AM -0700, Daniele Ceraolo Spurio wrote:
> The GSCCS has its own enable and mask registers. The interrupt identity
> for the GSCCS shows OTHER_CLASS instance 6.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

Register offsets match documentation at bspec 54029 / 54030.  Other
changes all look correct for handling enabling/masking in the right
places.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_irq.c          | 25 ++++++++++++++++++-------
>  2 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 69c188999e73..e3d1cec7ba8d 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -383,6 +383,7 @@
>  
>  #define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030)
>  #define VCS_VECS_INTR_ENABLE			XE_REG(0x190034)
> +#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044)
>  #define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048)
>  #define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4))
>  #define RCS0_RSVD_INTR_MASK			XE_REG(0x190090)
> @@ -392,6 +393,7 @@
>  #define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0)
>  #define GUC_SG_INTR_MASK			XE_REG(0x1900e8)
>  #define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec)
> +#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4)
>  #define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
>  #define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
>  #define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 2022a5643e01..1dee3e832eb5 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -176,6 +176,11 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
>  		xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
>  		xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
> +
> +		if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) {
> +			xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, irqs);
> +			xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~irqs);
> +		}
>  	}
>  }
>  
> @@ -244,7 +249,7 @@ static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
>  		return tile->media_gt;
>  
>  	if (class == XE_ENGINE_CLASS_OTHER &&
> -	    instance == OTHER_MEDIA_GUC_INSTANCE)
> +	    (instance == OTHER_MEDIA_GUC_INSTANCE || instance == OTHER_GSC_INSTANCE))
>  		return tile->media_gt;
>  
>  	return tile->primary_gt;
> @@ -281,16 +286,16 @@ static void gt_irq_handler(struct xe_tile *tile,
>  
>  			engine_gt = pick_engine_gt(tile, class, instance);
>  
> -			if (class == XE_ENGINE_CLASS_OTHER) {
> -				gt_other_irq_handler(engine_gt, instance, intr_vec);
> +			hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
> +			if (hwe) {
> +				xe_hw_engine_handle_irq(hwe, intr_vec);
>  				continue;
>  			}
>  
> -			hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
> -			if (!hwe)
> +			if (class == XE_ENGINE_CLASS_OTHER) {
> +				gt_other_irq_handler(engine_gt, instance, intr_vec);
>  				continue;
> -
> -			xe_hw_engine_handle_irq(hwe, intr_vec);
> +			}
>  		}
>  	}
>  
> @@ -465,6 +470,12 @@ static void gt_irq_reset(struct xe_tile *tile)
>  	if (ccs_mask & (BIT(2)|BIT(3)))
>  		xe_mmio_write32(mmio,  CCS2_CCS3_INTR_MASK, ~0);
>  
> +	if (tile->media_gt &&
> +	    xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) {
> +		xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0);
> +		xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0);
> +	}
> +
>  	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
>  	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK,  ~0);
>  	xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE,	 0);
> -- 
> 2.41.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation