[Intel-xe] [PATCH 4/6] drm/xe: add GSCCS ring ops

[Matt Roper]

On Wed, Aug 16, 2023 at 11:04:23AM -0700, Daniele Ceraolo Spurio wrote:
> Like the BCS, the GSCCS doesn't have any special HW that needs handling
> when emitting commands, so we can re-use the same emit_job code. To make
> it clear that this is now a shared low-level function, it has been
> renamed to use the "simple" postfix, instead of "copy", to indicate that
> it applies to all engines that don't need any additional engine-specific
> handling.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

GSCCS changes look okay, although this does make me realize that we
probably need to update the BCS handling to do aux invalidation on MTL.
But that's not important to this series.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_ring_ops.c | 26 +++++++++++++++++++++-----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 4a474ab04f96..11a089ae79b2 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -205,8 +205,9 @@ static u32 get_ppgtt_flag(struct xe_sched_job *job)
>  	return !(job->q->flags & EXEC_QUEUE_FLAG_WA) ? BIT(8) : 0;
>  }
>  
> -static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc,
> -				  u64 batch_addr, u32 seqno)
> +/* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
> +static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,
> +				    u64 batch_addr, u32 seqno)
>  {
>  	u32 dw[MAX_JOB_SIZE_DW], i = 0;
>  	u32 ppgtt_flag = get_ppgtt_flag(job);
> @@ -374,6 +375,15 @@ static void emit_migration_job_gen12(struct xe_sched_job *job,
>  	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
>  }
>  
> +static void emit_job_gen12_gsc(struct xe_sched_job *job)
> +{
> +	XE_WARN_ON(job->q->width > 1); /* no parallel submission for GSCCS */
> +
> +	__emit_job_gen12_simple(job, job->q->lrc,
> +				job->batch_addr[0],
> +				xe_sched_job_seqno(job));
> +}
> +
>  static void emit_job_gen12_copy(struct xe_sched_job *job)
>  {
>  	int i;
> @@ -385,9 +395,9 @@ static void emit_job_gen12_copy(struct xe_sched_job *job)
>  	}
>  
>  	for (i = 0; i < job->q->width; ++i)
> -		__emit_job_gen12_copy(job, job->q->lrc + i,
> -				      job->batch_addr[i],
> -				      xe_sched_job_seqno(job));
> +		__emit_job_gen12_simple(job, job->q->lrc + i,
> +				        job->batch_addr[i],
> +				        xe_sched_job_seqno(job));
>  }
>  
>  static void emit_job_gen12_video(struct xe_sched_job *job)
> @@ -411,6 +421,10 @@ static void emit_job_gen12_render_compute(struct xe_sched_job *job)
>  						xe_sched_job_seqno(job));
>  }
>  
> +static const struct xe_ring_ops ring_ops_gen12_gsc = {
> +	.emit_job = emit_job_gen12_gsc,
> +};
> +
>  static const struct xe_ring_ops ring_ops_gen12_copy = {
>  	.emit_job = emit_job_gen12_copy,
>  };
> @@ -427,6 +441,8 @@ const struct xe_ring_ops *
>  xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class)
>  {
>  	switch (class) {
> +	case XE_ENGINE_CLASS_OTHER:
> +		return &ring_ops_gen12_gsc;
>  	case XE_ENGINE_CLASS_COPY:
>  		return &ring_ops_gen12_copy;
>  	case XE_ENGINE_CLASS_VIDEO_DECODE:
> -- 
> 2.41.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation