[Intel-xe] [PATCH v2 2/3] drm/xe/pvc: Force even num engines to use 64B

[Niranjana Vishwanathapura]

On Thu, Aug 17, 2023 at 09:22:17AM -0700, Matt Roper wrote:
>On Thu, Aug 17, 2023 at 04:03:51AM -0700, Niranjana Vishwanathapura wrote:
>> Wa_16017236439 requires that we update BCS_SWCTRL
>> (via indirect context batch buffer) to set 64B
>> transfers when running on an even-numbered BCS
>> engine and 256B on an odd-numbered BCS engine.
>>
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 3 +++
>>  drivers/gpu/drm/xe/xe_wa.c               | 7 +++++++
>>  2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> index 79873bf64e8d..8e488cbe332b 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> @@ -59,6 +59,9 @@
>>  #define RING_BBADDR(base)			XE_REG((base) + 0x140)
>>  #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
>>
>> +#define BCS_ENGINE_SWCTL(base)                 XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
>> +#define BCS_ENGINE_SWCTL_DISABLE_256B          REG_BIT(2)
>> +
>>  /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
>>  #define BLIT_CCTL(base)				XE_REG((base) + 0x204)
>>  #define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index e2b6e17d7ec4..e7b8cbbaf002 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -515,6 +515,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>>  		       GRAPHICS_STEP(B0, C0)),
>>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
>>  	},
>> +	{ XE_RTP_NAME("16017236439"),
>> +	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
>> +		       FUNC(xe_rtp_match_even_instance)),
>> +	  XE_RTP_ACTIONS(SET(BCS_ENGINE_SWCTL(0),
>
>According to bspec 53978, this register is part of the BCS engine's
>context (when searching the page, they spell it as "SWCTRL" rather than
>"SWCTL").  That means we should add this change to lrc_was[] instead of
>engine_was[].
>

Got it. Will move it to lrc_was[].

Niranjana

>
>Matt
>
>> +			     BCS_ENGINE_SWCTL_DISABLE_256B,
>> +			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),
>> +	},
>>
>>  	/* Xe_LPG */
>>  	{ XE_RTP_NAME("14017856879"),
>> --
>> 2.21.0.rc0.32.g243a4c7e27
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation