[Intel-xe] [PATCH v2 08/15] drm/xe/xe2: Define Xe2_LPG IP features

[Lucas De Marchi]

On Mon, Aug 21, 2023 at 08:28:45PM +0530, Balasubramani Vivekanandan wrote:
>On 18.08.2023 15:08, Lucas De Marchi wrote:
>> From: Matt Roper <matthew.d.roper at intel.com>
>>
>> Define a common set of Xe2 graphics feature flags and definitions that
>> will be used for all platforms in this family.
>>
>> Several of the feature flags are inherited unchanged from Xe_HP and/or
>> Xe_HPC platforms:
>>  - dma_mask_size remains 46   (Bspec 70817)
>>  - supports_usm=1             (Bspec 59651)
>>  - has_flatccs=1              (Bspec 58797)
>>  - has_asid=1                 (Bspec 59654, 59265, 60288)
>>  - has_range_tlb_invalidate=1 (Bspec 71126)
>>
>> However some of them still need proper implementation in the driver to
>> be used, so they are disabled.
>>
>> Notable Xe2-specific changes:
>>  - All Xe2 platforms use a five-level page table, regardless of the
>>    virtual address space for the platform.  (Bspec 59505)
>>
>> The graphics engine mask represents the Xe2 architecture engines (Bspec
>> 60149), but individual platforms may have a reduced set of usable
>> engines, as reflected by their fusing.
>>
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_pci.c | 19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 46e3a9632efe..ed6c4bf8c63b 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -176,6 +176,24 @@ static const struct xe_graphics_desc graphics_xelpg = {
>>  	.has_flat_ccs = 0,
>>  };
>>
>> +#define XE2_GFX_FEATURES \
>> +	.dma_mask_size = 46, \
>> +	.has_asid = 1, \
>> +	.has_flat_ccs = 0 /* FIXME: implementation missing */, \
>> +	.has_range_tlb_invalidation = 1, \
>> +	.supports_usm = 0 /* FIXME: implementation missing */, \
>> +	.vm_max_level = 4, \
>> +	.hw_engine_mask = \
>> +		BIT(XE_HW_ENGINE_RCS0) | \
>> +		BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
>> +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
>
>Bspec: 60149 lists more BCS engines than what is assigned here. Is it
>intentionally limited to only BCS0, BCS8.

That's only the mmio address offsets allocated, it doesn't mean the
platform has those engines. See BSpec 70815: there's one main copy
engine and one paging copy engine.

Lucas De Marchi

>
>Regards,
>Bala
>
>> +
>> +static const struct xe_graphics_desc graphics_xe2 = {
>> +	.name = "Xe2_LPG",
>> +
>> +	XE2_GFX_FEATURES,
>> +};
>> +
>>  static const struct xe_media_desc media_xem = {
>>  	.name = "Xe_M",
>>  	.ver = 12,
>> @@ -320,6 +338,7 @@ __diag_pop();
>>  static struct gmdid_map graphics_ip_map[] = {
>>  	{ 1270, &graphics_xelpg },
>>  	{ 1271, &graphics_xelpg },
>> +	{ 2004, &graphics_xe2 },
>>  };
>>
>>  /* Map of GMD_ID values to media IP */
>> --
>> 2.40.1
>>