[Intel-xe] ✓ CI.Patch_applied: success for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 8ca78f69c drm/xe: Drop xe_mmio_write64()
=== git am output follows ===
Applying: drm/i915: Start using plane scale factor for relative data rate
Applying: drm/i915/display: Remove unused POWER_DOMAIN_MASK
Applying: drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
Applying: drm/i915: Simplify intel_cx0_program_phy_lane() with loop
Applying: drm/i915/cx0: Enable/disable TX only for owned PHY lanes
Applying: drm/i915/cx0: Program vswing only for owned lanes
Applying: drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
Applying: drm/i915/tc: make intel_tc_port_get_lane_mask() static
Applying: drm/i915/tc: move legacy code out of the main _max_lane_count() func
Applying: drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
Applying: drm/xe/lnl: Add IS_LUNARLAKE
Applying: drm/i915/lnl: Add display definitions
Applying: drm/i915: Re-order if/else ladder in intel_detect_pch()
Applying: drm/i915/lnl: Add fake PCH
Applying: drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
Applying: drm/i915/xe2lpd: Move D2D enable/disable
Applying: drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
Applying: drm/i915/xe2lpd: Move registers to PICA
Applying: drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
Applying: drm/i915/xe2lpd: Register DE_RRMR has been removed
Applying: drm/i915/xe2lpd: Add display power well
Applying: drm/i915/xe2lpd: Add DC state support
Applying: drm/i915/xe2lpd: FBC is now supported on all pipes
Applying: drm/i915/display: Remove FBC capability from fused off pipes
Applying: drm/i915/xe2lpd: Add support for DP aux channels
Applying: drm/i915/xe2lpd: Handle port AUX interrupts
Applying: drm/i915/xe2lpd: Read pin assignment from IOM
Applying: drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
Applying: drm/i915/xe2lpd: Add support for HPD
Applying: drm/i915/xe2lpd: Extend Wa_15010685871
Applying: drm/i915/lnl: Add gmbus/ddc support
Applying: drm/i915/lnl: Introduce MDCLK
Applying: drm/i915/lnl: Add CDCLK table
Applying: drm/i915/lnl: Start using CDCLK through PLL
Applying: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
Applying: drm/i915/lnl: Add support for CDCLK initialization sequence
Applying: drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
Applying: drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
Applying: drm/i915/lnl: Add pll table for LNL platform
Applying: drm/i915/lnl: Add support to check c10 phy link rate
Applying: drm/i915/xe2lpd: Update mbus on post plane updates
Applying: drm/xe/lnl: Enable the display support