[Intel-xe] [PATCH 1/4] drm/i915/lnl: FBC can be enabled with PSR2

Matt Roper matthew.d.roper at intel.com
Mon Aug 28 23:58:01 UTC 2023


On Mon, Aug 28, 2023 at 09:20:32AM +0300, Vinod Govindapillai wrote:
> FBC restriction with PSR2 can be removed from LNL onwards
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 66c8aed07bbc..d36499d7e0be 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1169,11 +1169,11 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>  	}
>  
>  	/*
> -	 * Display 12+ is not supporting FBC with PSR2.
> +	 * Display 12 to 14 is not supporting FBC with PSR2.
>  	 * Recommendation is to keep this combination disabled
>  	 * Bspec: 50422 HSD: 14010260002
>  	 */
> -	if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
> +	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {

According to bspec 68881, the situation is more complicated than just
flipping this back on.  FBC + PSR2 should only be enabled together if a
bunch of other conditions are met (multiple planes enabled, selective
fetch is not enabled, etc.).  Otherwise we may be hurting power usage
rather than helping it by turning these two on together.


Matt

>  		plane_state->no_fbc_reason = "PSR2 enabled";
>  		return 0;
>  	}
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation


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