[Intel-xe] [PATCH] drm/xe/xe2: Add workaround 18032095049

[Tejas Upadhyay]

This workaround applies to graphics 20.04 A0 step and on
render engine

Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h |  9 +++++++++
 drivers/gpu/drm/xe/xe_wa.c               | 10 ++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 444ff9b83bb1..5f70eb62db70 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -40,6 +40,10 @@
 #define RING_NOPID(base)			XE_REG((base) + 0x94)
 
 #define RING_IMR(base)				XE_REG((base) + 0xa8)
+#define   RENDER_INTR_VEC			REG_GENMASK(15, 0)
+#define   RENDER_INTR_VEC_PIPE_CONTROL_NOTIFY	REG_BIT(4)
+#define   RENDER_INTR_VEC_MI_USER_INTERRUPT	REG_BIT(0)
+
 #define   RING_MAX_NONPRIV_SLOTS  12
 
 #define RING_EIR(base)				XE_REG((base) + 0xb0)
@@ -47,6 +51,11 @@
 #define RING_ESR(base)				XE_REG((base) + 0xb8)
 
 #define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
+
+#define CSFE_CHICKEN1_REG(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
+#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
+#define   GHWSP_CSB_REPORT_DISABLE		REG_BIT(15)
+
 /*
  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
  * The lsb of each can be considered a separate enabling bit for encryption.
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 63bd4bb1af03..c5c640dcb427 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -596,6 +596,16 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
 	},
+	{ XE_RTP_NAME("18032095049"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(FIELD_SET(RING_IMR(0),
+				   RENDER_INTR_VEC,
+				   RENDER_INTR_VEC_PIPE_CONTROL_NOTIFY |
+				   RENDER_INTR_VEC_MI_USER_INTERRUPT,
+				   XE_RTP_ACTION_FLAG(ENGINE_BASE)),
+			 SET(CSFE_CHICKEN1_REG(0), PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS |
+			     GHWSP_CSB_REPORT_DISABLE))
+	},
 
 	{}
 };
-- 
2.25.1