[Intel-xe] ✗ CI.checkpatch: warning for drm/xe/xe2: Add workaround 18032095049 (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe/xe2: Add workaround 18032095049 (rev2)
URL   : https://patchwork.freedesktop.org/series/127304/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6030b24c1386b00de8187b5fb987e283a57b372a
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 447775bb4d61e73c87c7fb04e8c3d13b43743772
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Tue Dec 5 14:22:49 2023 +0530

    drm/xe/xe2: Add workaround 18032095049
    
    This workaround applies to graphics 20.04 A0 step and on
    render engine.
    
    Workaround has three parts :
    1. Pipe flush before MI_ATOMIC - This part isn't relevant to Xe
       (at least not right now) since we don't use MI_ATOMIC anywhere
       in the kernel mode driver.
    2. Memory-based interrupt masking - Memory-based interrupt processing
       isn't supported on physical functions, only virtual functions,
       according to bspec 60352. So this is probably only relevant once
       SRIOV support lands in the driver.
    3. Disabling CSB/timestamp updates to the ghwsp and pphwsp - Workaround
       is added by this change.
    
    V2(MattR):
      - Mention detail in commit message
      - Reorder bit define
      - Improve bit naming
      - Remove workaround part which isnt relevant
    
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch 2c3aa5d8d87f6026a9fb60d2d78a9f4114722e24 drm-intel
447775bb4 drm/xe/xe2: Add workaround 18032095049
-:24: WARNING:TYPO_SPELLING: 'isnt' may be misspelled - perhaps 'isn't'?
#24: 
  - Remove workaround part which isnt relevant
                                 ^^^^

total: 0 errors, 1 warnings, 0 checks, 30 lines checked