[Intel-xe] ✓ CI.checkpatch: success for drm/xe/xe2: Add workaround 16021639441

[Patchwork]

== Series Details ==

Series: drm/xe/xe2: Add workaround 16021639441
URL   : https://patchwork.freedesktop.org/series/127357/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6030b24c1386b00de8187b5fb987e283a57b372a
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6d14ce7a7cc6367b2739b9433cfbf66a149804e5
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Tue Dec 5 18:47:16 2023 +0530

    drm/xe/xe2: Add workaround 16021639441
    
    This workaround applies to graphics 20.04 and on
    non render engine.
    
    Workaround has three parts :
    1. Pipe flush before MI_ATOMIC - This part isn't relevant to Xe
       (at least not right now) since we don't use MI_ATOMIC anywhere
       in the kernel mode driver.
    2. Memory-based interrupt masking - Memory-based interrupt processing
       isn't supported on physical functions, only virtual functions,
       according to bspec 60352. So this is probably only relevant once
       SRIOV support lands in the driver.
    3. Disabling CSB/timestamp updates to the ghwsp and pphwsp - Workaround
       is added by this change.
    
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch ac7b89571d802765762e7c15d78a6dcd5d92c41b drm-intel
6d14ce7a7 drm/xe/xe2: Add workaround 16021639441