[Intel-xe] [PATCH V2] drm/xe/xe2: Add workaround 18032095049

[Matt Roper]

On Tue, Dec 05, 2023 at 02:22:49PM +0530, Tejas Upadhyay wrote:
> This workaround applies to graphics 20.04 A0 step and on
> render engine.
> 
> Workaround has three parts :
> 1. Pipe flush before MI_ATOMIC - This part isn't relevant to Xe
>    (at least not right now) since we don't use MI_ATOMIC anywhere
>    in the kernel mode driver.
> 2. Memory-based interrupt masking - Memory-based interrupt processing
>    isn't supported on physical functions, only virtual functions,
>    according to bspec 60352. So this is probably only relevant once
>    SRIOV support lands in the driver.
> 3. Disabling CSB/timestamp updates to the ghwsp and pphwsp - Workaround
>    is added by this change.
> 
> V2(MattR):
>   - Mention detail in commit message
>   - Reorder bit define
>   - Improve bit naming
>   - Remove workaround part which isnt relevant
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 6 ++++++
>  drivers/gpu/drm/xe/xe_wa.c               | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 444ff9b83bb1..ecdbc04a2d91 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -40,6 +40,7 @@
>  #define RING_NOPID(base)			XE_REG((base) + 0x94)
>  
>  #define RING_IMR(base)				XE_REG((base) + 0xa8)
> +
>  #define   RING_MAX_NONPRIV_SLOTS  12

Unintended change?  Even though RING_MAX_NONPRIV_SLOTS doesn't seem to
belong here at all (it's defined twice in the header, probably due to a
conflict resolution mistake at some point), but that should be cleaned
up independently in a separate patch.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

>  
>  #define RING_EIR(base)				XE_REG((base) + 0xb0)
> @@ -47,6 +48,11 @@
>  #define RING_ESR(base)				XE_REG((base) + 0xb8)
>  
>  #define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
> +
> +#define CSFE_CHICKEN1_REG(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
> +#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)
> +#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
> +
>  /*
>   * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
>   * The lsb of each can be considered a separate enabling bit for encryption.
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 63bd4bb1af03..4389ce3548dd 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -596,6 +596,12 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
>  	},
> +	{ XE_RTP_NAME("18032095049"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0),
> +			     GHWSP_CSB_REPORT_DIS |
> +			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS))
> +	},
>  
>  	{}
>  };
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation