[Intel-xe] [PATCH] drm/xe/xe2: Add workaround 16021639441
Upadhyay, Tejas
tejas.upadhyay at intel.com
Wed Dec 6 04:29:18 UTC 2023
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper at intel.com>
> Sent: Wednesday, December 6, 2023 3:42 AM
> To: Upadhyay, Tejas <tejas.upadhyay at intel.com>
> Cc: intel-xe at lists.freedesktop.org
> Subject: Re: [PATCH] drm/xe/xe2: Add workaround 16021639441
>
> On Tue, Dec 05, 2023 at 06:47:16PM +0530, Tejas Upadhyay wrote:
> > This workaround applies to graphics 20.04 and on non render engine.
> >
> > Workaround has three parts :
> > 1. Pipe flush before MI_ATOMIC - This part isn't relevant to Xe
> > (at least not right now) since we don't use MI_ATOMIC anywhere
> > in the kernel mode driver.
> > 2. Memory-based interrupt masking - Memory-based interrupt processing
> > isn't supported on physical functions, only virtual functions,
> > according to bspec 60352. So this is probably only relevant once
> > SRIOV support lands in the driver.
> > 3. Disabling CSB/timestamp updates to the ghwsp and pphwsp -
> Workaround
> > is added by this change.
>
> This workaround is basically the inverse of Wa_18032095049; that one
> applies to RCS and this one applies to the other engines. The difference is
> that the RCS engine workaround is a temporary workaround needed only for
> a-step, while this one applies to all steppings.
>
> The CSB reports to gHWSP and ppHWSP have been discussed as part of a
> different topic on some internal threads and we've confirmed that neither the
> KMD nor the GuC firmware use those for anything, so disabling them is
> always "safe" and should have no functional or performance impact on
> system operation. I expect the same is true for the timestamp updates in the
> ppHWSP as well. Given that, it might make sense to just combine these two
> workarounds into a single record (and single patch) and apply it on all
> steppings. Disabling the reports for RCS on higher steppings doesn't have any
> kind of negative impact and will simplify the overall situation. E.g.,
>
> /*
> * These two workarounds are the same, just applying to different
> * engines. Although Wa_18032095049 (for the RCS) isn't required on
> * all steppings, disabling these reports has no impact for our
> * driver or the GuC, so we go ahead and treat it the same as
> * Wa_16021639441 which does apply to all steppings.
> */
> { XE_RTP_NAME("18032095049 / 16021639441"),
> XE_RTP_RULES(GRAPHICS_VERSION(2004)),
> XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0),
> GHWSP_CSB_REPORT_DIS |
> PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> XE_RTP_ACTION_FLAG(ENGINE_BASE))),
> },
Got it, it makes sense if disabling on B0 stepping for RCS has no impact. I will make this as combine patch as mentioned above.
Tejas
>
> >
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
> > ---
> > drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++++
> > drivers/gpu/drm/xe/xe_rtp.c | 6 ++++++
> > drivers/gpu/drm/xe/xe_rtp.h | 10 ++++++++++
> > drivers/gpu/drm/xe/xe_wa.c | 7 +++++++
> > 4 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > index 444ff9b83bb1..0875b2cc0f01 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > @@ -47,6 +47,10 @@
> > #define RING_ESR(base) XE_REG((base) +
> 0xb8)
> >
> > #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4,
> XE_REG_OPTION_MASKED)
> > +
> > +#define CSFE_CHICKEN1_REG(base) XE_REG((base) +
> 0xd4, XE_REG_OPTION_MASKED)
> > +#define GHWSP_CSB_REPORT_DIS REG_BIT(15)
> > +#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
> > /*
> > * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
> > * The lsb of each can be considered a separate enabling bit for encryption.
> > diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> > index fb44cc7521d8..e84e08a66af3 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.c
> > +++ b/drivers/gpu/drm/xe/xe_rtp.c
> > @@ -309,6 +309,12 @@ bool
> xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
> > hwe->engine_id == __ffs(render_compute_mask); }
> >
> > +bool xe_rtp_match_non_render(const struct xe_gt *gt,
> > + const struct xe_hw_engine *hwe) {
> > + return hwe->class == XE_ENGINE_CLASS_RENDER ? false : true; }
> > +
> > bool xe_rtp_match_first_gslice_fused_off(const struct xe_gt *gt,
> > const struct xe_hw_engine *hwe) {
> diff --git
> > a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h index
> > c56fedd126e6..a30f89d80046 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.h
> > +++ b/drivers/gpu/drm/xe/xe_rtp.h
> > @@ -427,4 +427,14 @@ bool
> xe_rtp_match_first_render_or_compute(const
> > struct xe_gt *gt, bool xe_rtp_match_first_gslice_fused_off(const struct
> xe_gt *gt,
> > const struct xe_hw_engine *hwe);
> >
> > +/*
> > + * xe_rtp_match_non_render - Match when non render engine in GT
> > + *
> > + * @gt: GT structure
> > + * @hwe: Engine instance
> > + *
> > + * Returns: true if engine is not render, false otherwise.
> > + */
> > +bool xe_rtp_match_non_render(const struct xe_gt *gt,
> > + const struct xe_hw_engine *hwe);
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> > index 63bd4bb1af03..45a910fe0141 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -596,6 +596,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> > XE_RTP_RULES(GRAPHICS_VERSION(2004),
> FUNC(xe_rtp_match_first_render_or_compute)),
> > XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
> > },
> > + { XE_RTP_NAME("16021639441"),
> > + XE_RTP_RULES(GRAPHICS_VERSION(2004),
> > + FUNC(xe_rtp_match_non_render)),
> > + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0),
> > + GHWSP_CSB_REPORT_DIS |
> > + PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS))
>
> The RTP engine base flag is needed here (also pointed out on the other
> workaround's patch).
>
>
> Matt
>
> > + },
> >
> > {}
> > };
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
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