[PATCH] drm/xe/xe2: Add workaround 16020183090

[Matt Roper]

On Thu, Dec 07, 2023 at 09:51:17AM -0800, Lucas De Marchi wrote:
> Graphics version 20.04, used in Lunar Lake, needs WA 16020183090 for
> steppings A*. Set ENABLE_SEMAPHORE_POLL_BIT in INSTPM(RENDER_RING_BASE)
> and whitelist CSBE_DEBUG_STATUS for userspace to be able to use it
> and complement the workaround.
> 
> Cc: Haridhar Kalvala <haridhar.kalvala at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++++
>  drivers/gpu/drm/xe/xe_reg_whitelist.c    | 8 ++++++++
>  drivers/gpu/drm/xe/xe_wa.c               | 5 +++++
>  3 files changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 3942db268b01..93d83ceba873 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -46,6 +46,9 @@
>  #define RING_EMR(base)				XE_REG((base) + 0xb4)
>  #define RING_ESR(base)				XE_REG((base) + 0xb8)
>  
> +#define INSTPM(base)				XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)
> +#define   ENABLE_SEMAPHORE_POLL_BIT		REG_BIT(13)
> +
>  #define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
>  
>  #define CSFE_CHICKEN1_REG(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
> @@ -92,6 +95,7 @@
>  #define   TAIL_ADDR				0x001FFFF8
>  
>  #define RING_CTX_TIMESTAMP(base)		XE_REG((base) + 0x3a8)
> +#define CSBE_DEBUG_STATUS(base)			XE_REG((base) + 0x3fc)
>  
>  #define RING_FORCE_TO_NONPRIV(base, i)		XE_REG(((base) + 0x4d0) + (i) * 4)
>  #define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index e66ae1bdaf9c..3fa2ece7d228 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -7,9 +7,11 @@
>  
>  #include "regs/xe_engine_regs.h"
>  #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
>  #include "xe_gt_types.h"
>  #include "xe_platform_types.h"
>  #include "xe_rtp.h"
> +#include "xe_step.h"
>  
>  #undef XE_REG_MCR
>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
> @@ -56,6 +58,12 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>  				   RING_FORCE_TO_NONPRIV_DENY,
>  				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
> +	{ XE_RTP_NAME("16020183090"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
> +		       ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))

For the userspace steps of this workaround, it sounds like they only
really need RO access to this register rather than RW.  Should we use
RING_FORCE_TO_NONPRIV_ACCESS_RD?  I guess it doesn't really matter too
much since the register itself is RO so even if userspace tries to write
to it nothing should happen.

Up to you whether it's worth explicitly flagging it RO here or not;
either way,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> +	},
> +
>  	{}
>  };
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 23f1285135b8..f3326825bef5 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -737,6 +737,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
>  	},
> +	{ XE_RTP_NAME("16020183090"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
> +		       ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
> +	},
>  
>  	{}
>  };
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation