[PATCH v7 04/10] drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT

[Matt Roper]

On Mon, Dec 11, 2023 at 07:13:50PM +0530, Himal Prasad Ghimiray wrote:
> - The XY_CTRL_SURF_COPY_BLT instruction operationg on ccs data expects

s/operationg/operating/

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> size in pages of main memory for which CCS data should be copied.
> - The bitfield representing copy size in XY_CTRL_SURF_COPY_BLT has
> shifted one bit higher in the instruction.
> 
> v2:
>  - Fix the num_pages for ccs size calculation.
>  - Address nits (Thomas)
> 
> v3:
> - Use FIELD_PREP and FIELD_FIT instead of shifts and numbers.(Matt)
> 
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Reviewed-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gpu_commands.h |  5 ++---
>  drivers/gpu/drm/xe/xe_migrate.c           | 21 +++++++++++++++------
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> index 1f9c32e694c6..a255946b6f77 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> @@ -11,13 +11,12 @@
>  #define XY_CTRL_SURF_COPY_BLT		((2 << 29) | (0x48 << 22) | 3)
>  #define   SRC_ACCESS_TYPE_SHIFT		21
>  #define   DST_ACCESS_TYPE_SHIFT		20
> -#define   CCS_SIZE_MASK			0x3FF
> -#define   CCS_SIZE_SHIFT		8
> +#define   CCS_SIZE_MASK			GENMASK(17, 8)
> +#define   XE2_CCS_SIZE_MASK		GENMASK(18, 9)
>  #define   XY_CTRL_SURF_MOCS_MASK	GENMASK(31, 26)
>  #define   XE2_XY_CTRL_SURF_MOCS_INDEX_MASK	GENMASK(31, 28)
>  #define   NUM_CCS_BYTES_PER_BLOCK	256
>  #define   NUM_BYTES_PER_CCS_BYTE(_xe)	(GRAPHICS_VER(_xe) >= 20 ? 512 : 256)
> -#define   NUM_CCS_BLKS_PER_XFER		1024
>  
>  #define XY_FAST_COLOR_BLT_CMD		(2 << 29 | 0x44 << 22)
>  #define   XY_FAST_COLOR_BLT_DEPTH_32	(2 << 19)
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index be2a92dee52c..cb9f00697115 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -526,21 +526,30 @@ static void emit_copy_ccs(struct xe_gt *gt, struct xe_bb *bb,
>  	struct xe_device *xe = gt_to_xe(gt);
>  	u32 *cs = bb->cs + bb->len;
>  	u32 num_ccs_blks;
> +	u32 num_pages;
> +	u32 ccs_copy_size;
>  	u32 mocs;
>  
> -	num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
> -				    NUM_CCS_BYTES_PER_BLOCK);
> -	xe_gt_assert(gt, num_ccs_blks <= NUM_CCS_BLKS_PER_XFER);
> +	if (GRAPHICS_VERx100(xe) >= 2000) {
> +		num_pages = DIV_ROUND_UP(size, XE_PAGE_SIZE);
> +		xe_gt_assert(gt, FIELD_FIT(XE2_CCS_SIZE_MASK, num_pages - 1));
>  
> -	if (GRAPHICS_VERx100(xe) >= 2000)
> +		ccs_copy_size = REG_FIELD_PREP(XE2_CCS_SIZE_MASK, num_pages - 1);
>  		mocs = FIELD_PREP(XE2_XY_CTRL_SURF_MOCS_INDEX_MASK, gt->mocs.uc_index);
> -	else
> +
> +	} else {
> +		num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
> +					    NUM_CCS_BYTES_PER_BLOCK);
> +		xe_gt_assert(gt, FIELD_FIT(CCS_SIZE_MASK, num_ccs_blks - 1));
> +
> +		ccs_copy_size = REG_FIELD_PREP(CCS_SIZE_MASK, num_ccs_blks - 1);
>  		mocs = FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, gt->mocs.uc_index);
> +	}
>  
>  	*cs++ = XY_CTRL_SURF_COPY_BLT |
>  		(src_is_indirect ? 0x0 : 0x1) << SRC_ACCESS_TYPE_SHIFT |
>  		(dst_is_indirect ? 0x0 : 0x1) << DST_ACCESS_TYPE_SHIFT |
> -		((num_ccs_blks - 1) & CCS_SIZE_MASK) << CCS_SIZE_SHIFT;
> +		ccs_copy_size;
>  	*cs++ = lower_32_bits(src_ofs);
>  	*cs++ = upper_32_bits(src_ofs) | mocs;
>  	*cs++ = lower_32_bits(dst_ofs);
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation