[PATCH 01/10] drm/xe: Add device flag for memory based IRQ support

[Matt Roper]

On Tue, Dec 12, 2023 at 10:00:45PM +0100, Michal Wajdeczko wrote:
> The register based interrupts infrastructure does not scale
> efficiently to allow delivering interrupts to a large number
> of virtual machines. Memory based interrupt reporting provides
> an efficient and scalable infrastructure.
> 
> Define device flag to indicate which platforms will use memory
> based interrupts for delivering interrupts to VFs.

It doesn't look like this flag actually gets set on any devices in this
series.  If I'm reading correctly, this flag should apply to every
platform with Xe_HP IP onward, right?  Do we expect there to ever be
future platforms that don't support memory-based IRQ?  If not, I'm not
sure if we even really need this feature flag and we could just do

        static inline bool xe_device_has_memirq(struct xe_device *xe)
        {
        	return GRAPHICS_VERx100(xe) >= 1250;
        }

instead?


Matt

> 
> Bspec: 50829
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.h       | 5 +++++
>  drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>  drivers/gpu/drm/xe/xe_pci.c          | 2 ++
>  3 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 3da83b233206..0b158d0d04e4 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -168,6 +168,11 @@ static inline bool xe_device_has_sriov(struct xe_device *xe)
>  	return xe->info.has_sriov;
>  }
>  
> +static inline bool xe_device_has_memirq(struct xe_device *xe)
> +{
> +	return xe->info.has_memirq;
> +}
> +
>  u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index d1a48456e9a3..0c48e3686837 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -259,6 +259,8 @@ struct xe_device {
>  		u8 has_flat_ccs:1;
>  		/** @has_llc: Device has a shared CPU+GPU last level cache */
>  		u8 has_llc:1;
> +		/** @has_memirq: Using memory based IRQ */
> +		u8 has_memirq:1;
>  		/** @has_mmio_ext: Device has extra MMIO address range */
>  		u8 has_mmio_ext:1;
>  		/** @has_range_tlb_invalidation: Has range based TLB invalidations */
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 260e8a6034a7..11559669cb8a 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -64,6 +64,7 @@ struct xe_device_desc {
>  	u8 has_display:1;
>  	u8 has_heci_gscfi:1;
>  	u8 has_llc:1;
> +	u8 has_memirq:1;
>  	u8 has_mmio_ext:1;
>  	u8 has_sriov:1;
>  	u8 skip_guc_pc:1;
> @@ -551,6 +552,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	xe->info.is_dgfx = desc->is_dgfx;
>  	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>  	xe->info.has_llc = desc->has_llc;
> +	xe->info.has_memirq = desc->has_memirq;
>  	xe->info.has_mmio_ext = desc->has_mmio_ext;
>  	xe->info.has_sriov = desc->has_sriov;
>  	xe->info.skip_guc_pc = desc->skip_guc_pc;
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation