[PATCH 02/10] drm/xe: Add command MI_LOAD_REGISTER_MEM

[Matt Roper]

On Tue, Dec 12, 2023 at 10:00:46PM +0100, Michal Wajdeczko wrote:
> We will need this shortly during context state preparation.

We should probably add decoding of this instruction to dump_mi_command()
in xe_lrc.c.  It looks like the Xe2 CSFE context includes a MI_LRM to
load the IRQ mask from context memory, so this command actually will
show up in our debugfs default_lrc entries.


Matt

> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index 1cfa96167fde..c74ceb550dce 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -56,6 +56,9 @@
>  #define   MI_FLUSH_IMM_QW		REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)
>  #define   MI_FLUSH_DW_USE_GTT		REG_BIT(2)
>  
> +#define MI_LOAD_REGISTER_MEM		(__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
> +#define   MI_LRM_USE_GGTT		REG_BIT(22)
> +
>  #define MI_BATCH_BUFFER_START		__MI_INSTR(0x31)
>  
>  #endif
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation