[PATCH 03/10] drm/xe: Define registers used by memory based irq processing

[Matt Roper]

On Tue, Dec 12, 2023 at 10:00:47PM +0100, Michal Wajdeczko wrote:
> The RING_INT_SRC_RPT_PTR register points to a cacheline in memory
> to which an engine must report as source of interrupt prior to
> generating an interrupt to the host.
> 
> The RING_INT_STATUS_RPT_PTR register points to the first cacheline
> of the Interrupt Status Report (ISR) page (4KB) in graphics memory
> to which all engines report their interrupt status.
> 
> The RING_IMR register has the interrupt enables and interrupt masks
> for an engine.
> 
> We will refer to these registers shortly.
> 
> Bspec: 45963, 45964, 45965
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

Unrelated to this patch, it looks like we have a stray/duplicate
RING_MAX_NONPRIV_SLOTS definition that shouldn't be there.  I'll send a
separate patch to drop that.


Matt

> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 3942db268b01..5e15c707e017 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -39,8 +39,10 @@
>  #define RING_MI_MODE(base)			XE_REG((base) + 0x9c)
>  #define RING_NOPID(base)			XE_REG((base) + 0x94)
>  
> +#define RING_INT_SRC_RPT_PTR(base)		XE_REG((base) + 0xa4)
>  #define RING_IMR(base)				XE_REG((base) + 0xa8)
>  #define   RING_MAX_NONPRIV_SLOTS  12
> +#define RING_INT_STATUS_RPT_PTR(base)		XE_REG((base) + 0xac)
>  
>  #define RING_EIR(base)				XE_REG((base) + 0xb0)
>  #define RING_EMR(base)				XE_REG((base) + 0xb4)
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation