[PATCH 04/10] drm/xe: Update LRC context layout definitions

[Matt Roper]

On Tue, Dec 12, 2023 at 10:00:48PM +0100, Michal Wajdeczko wrote:
> The new memory based interrupt processing uses additional entries
> in the context.  Add required definitions.
> 
> Bspec: 45585

You might want to add the Xe2 bspec page here as well (60184) since the
context layout is different.  The Xe2 page doesn't have the same handy
running dword tally that the Xe1 page has, and the stuff preceding the
MI_LRM has changed, but when I count up the dwords manually it does
indeed seem that the MI_LRM itself still winds up at the same 0x50
offset into the LRC, so

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> index 4be81abc86ad..1825d8f79db6 100644
> --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> @@ -14,4 +14,13 @@
>  #define CTX_PDP0_UDW			(0x30 + 1)
>  #define CTX_PDP0_LDW			(0x32 + 1)
>  
> +#define CTX_LRM_INT_MASK_ENABLE		0x50
> +#define CTX_INT_MASK_ENABLE_REG		(CTX_LRM_INT_MASK_ENABLE + 1)
> +#define CTX_INT_MASK_ENABLE_PTR		(CTX_LRM_INT_MASK_ENABLE + 2)
> +#define CTX_LRI_INT_REPORT_PTR		0x55
> +#define CTX_INT_STATUS_REPORT_REG	(CTX_LRI_INT_REPORT_PTR + 1)
> +#define CTX_INT_STATUS_REPORT_PTR	(CTX_LRI_INT_REPORT_PTR + 2)
> +#define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)
> +#define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)
> +
>  #endif
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation