[PATCH 05/10] drm/xe: Update definition of GT_INTR_DW

[Matt Roper]

On Tue, Dec 12, 2023 at 10:00:49PM +0100, Michal Wajdeczko wrote:
> Add bits definitions that we will be using in upcoming patch.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 5f5a72e9d0d8..f2562834ca59 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -437,6 +437,15 @@
>  #define   VOLTAGE_MASK				REG_GENMASK(10, 0)
>  
>  #define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4))
> +#define   INTR_GSC				REG_BIT(31)
> +#define   INTR_GUC				REG_BIT(25)
> +#define   MTL_INTR_MGUC				REG_BIT(24)
> +#define   XEHPC_INTR_BCS8			REG_BIT(23)

Personally I'd drop the "MTL_" and "XEHPC_" prefixes since these
registers are going to exist on every platform "officially" supported by
the Xe driver, and even for the older platforms we're using as
development vehicles right now, they don't clash with anything else
either.  Up to you though; the bit definitions here match the two
GT_INTR_DW registers, so

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> +#define   INTR_BCS(x)				REG_BIT(15 - (x))
> +#define   INTR_CCS(x)				REG_BIT(4 + (x))
> +#define   INTR_RCS0				REG_BIT(0)
> +#define   INTR_VECS(x)				REG_BIT(31 - (x))
> +#define   INTR_VCS(x)				REG_BIT(x)
>  
>  #define GUC_SG_INTR_ENABLE			XE_REG(0x190038)
>  #define   ENGINE1_MASK				REG_GENMASK(31, 16)
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation