[PATCH 06/10] drm/xe: Define IRQ offsets used by HW engines
Matt Roper
matthew.d.roper at intel.com
Tue Dec 12 22:43:09 UTC 2023
On Tue, Dec 12, 2023 at 10:00:50PM +0100, Michal Wajdeczko wrote:
> When interrupts are delivered using memory based mechanism, engines
> will write status to the report page at the offset that corresponds
You might want to say "offset (in bytes)" since otherwise it gets
confusing as to whether we're talking about bits, bytes, or dwords.
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> to their interrupt bit from the GT_INTR_DW register.
>
> Add engine interrupt offset definitions to engine info as we will
> need this to process memory based interrupts.
>
> Bspec: 46149, 50829, 50844
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 28 +++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_hw_engine_types.h | 2 ++
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 86b863b99065..ca35b1768a8a 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -35,6 +35,7 @@ struct engine_info {
> const char *name;
> unsigned int class : 8;
> unsigned int instance : 8;
> + unsigned int irq_offset : 8;
> enum xe_force_wake_domains domain;
> u32 mmio_base;
> };
> @@ -44,6 +45,7 @@ static const struct engine_info engine_infos[] = {
> .name = "rcs0",
> .class = XE_ENGINE_CLASS_RENDER,
> .instance = 0,
> + .irq_offset = ilog2(INTR_RCS0),
> .domain = XE_FW_RENDER,
> .mmio_base = RENDER_RING_BASE,
> },
> @@ -51,6 +53,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs0",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 0,
> + .irq_offset = ilog2(INTR_BCS(0)),
> .domain = XE_FW_RENDER,
> .mmio_base = BLT_RING_BASE,
> },
> @@ -58,6 +61,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs1",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 1,
> + .irq_offset = ilog2(INTR_BCS(1)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS1_RING_BASE,
> },
> @@ -65,6 +69,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs2",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 2,
> + .irq_offset = ilog2(INTR_BCS(2)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS2_RING_BASE,
> },
> @@ -72,6 +77,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs3",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 3,
> + .irq_offset = ilog2(INTR_BCS(3)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS3_RING_BASE,
> },
> @@ -79,6 +85,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs4",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 4,
> + .irq_offset = ilog2(INTR_BCS(4)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS4_RING_BASE,
> },
> @@ -86,6 +93,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs5",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 5,
> + .irq_offset = ilog2(INTR_BCS(5)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS5_RING_BASE,
> },
> @@ -93,12 +101,14 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs6",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 6,
> + .irq_offset = ilog2(INTR_BCS(6)),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS6_RING_BASE,
> },
> [XE_HW_ENGINE_BCS7] = {
> .name = "bcs7",
> .class = XE_ENGINE_CLASS_COPY,
> + .irq_offset = ilog2(INTR_BCS(7)),
> .instance = 7,
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS7_RING_BASE,
> @@ -107,6 +117,7 @@ static const struct engine_info engine_infos[] = {
> .name = "bcs8",
> .class = XE_ENGINE_CLASS_COPY,
> .instance = 8,
> + .irq_offset = ilog2(XEHPC_INTR_BCS8),
> .domain = XE_FW_RENDER,
> .mmio_base = XEHPC_BCS8_RING_BASE,
> },
> @@ -115,6 +126,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs0",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 0,
> + .irq_offset = 32 + ilog2(INTR_VCS(0)),
> .domain = XE_FW_MEDIA_VDBOX0,
> .mmio_base = BSD_RING_BASE,
> },
> @@ -122,6 +134,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs1",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 1,
> + .irq_offset = 32 + ilog2(INTR_VCS(1)),
> .domain = XE_FW_MEDIA_VDBOX1,
> .mmio_base = BSD2_RING_BASE,
> },
> @@ -129,6 +142,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs2",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 2,
> + .irq_offset = 32 + ilog2(INTR_VCS(2)),
> .domain = XE_FW_MEDIA_VDBOX2,
> .mmio_base = BSD3_RING_BASE,
> },
> @@ -136,6 +150,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs3",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 3,
> + .irq_offset = 32 + ilog2(INTR_VCS(3)),
> .domain = XE_FW_MEDIA_VDBOX3,
> .mmio_base = BSD4_RING_BASE,
> },
> @@ -143,6 +158,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs4",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 4,
> + .irq_offset = 32 + ilog2(INTR_VCS(4)),
> .domain = XE_FW_MEDIA_VDBOX4,
> .mmio_base = XEHP_BSD5_RING_BASE,
> },
> @@ -150,6 +166,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs5",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 5,
> + .irq_offset = 32 + ilog2(INTR_VCS(5)),
> .domain = XE_FW_MEDIA_VDBOX5,
> .mmio_base = XEHP_BSD6_RING_BASE,
> },
> @@ -157,6 +174,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs6",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 6,
> + .irq_offset = 32 + ilog2(INTR_VCS(6)),
> .domain = XE_FW_MEDIA_VDBOX6,
> .mmio_base = XEHP_BSD7_RING_BASE,
> },
> @@ -164,6 +182,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vcs7",
> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> .instance = 7,
> + .irq_offset = 32 + ilog2(INTR_VCS(7)),
> .domain = XE_FW_MEDIA_VDBOX7,
> .mmio_base = XEHP_BSD8_RING_BASE,
> },
> @@ -171,6 +190,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vecs0",
> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> .instance = 0,
> + .irq_offset = 32 + ilog2(INTR_VECS(0)),
> .domain = XE_FW_MEDIA_VEBOX0,
> .mmio_base = VEBOX_RING_BASE,
> },
> @@ -178,6 +198,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vecs1",
> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> .instance = 1,
> + .irq_offset = 32 + ilog2(INTR_VECS(1)),
> .domain = XE_FW_MEDIA_VEBOX1,
> .mmio_base = VEBOX2_RING_BASE,
> },
> @@ -185,6 +206,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vecs2",
> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> .instance = 2,
> + .irq_offset = 32 + ilog2(INTR_VECS(2)),
> .domain = XE_FW_MEDIA_VEBOX2,
> .mmio_base = XEHP_VEBOX3_RING_BASE,
> },
> @@ -192,6 +214,7 @@ static const struct engine_info engine_infos[] = {
> .name = "vecs3",
> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> .instance = 3,
> + .irq_offset = 32 + ilog2(INTR_VECS(3)),
> .domain = XE_FW_MEDIA_VEBOX3,
> .mmio_base = XEHP_VEBOX4_RING_BASE,
> },
> @@ -199,6 +222,7 @@ static const struct engine_info engine_infos[] = {
> .name = "ccs0",
> .class = XE_ENGINE_CLASS_COMPUTE,
> .instance = 0,
> + .irq_offset = ilog2(INTR_CCS(0)),
> .domain = XE_FW_RENDER,
> .mmio_base = COMPUTE0_RING_BASE,
> },
> @@ -206,6 +230,7 @@ static const struct engine_info engine_infos[] = {
> .name = "ccs1",
> .class = XE_ENGINE_CLASS_COMPUTE,
> .instance = 1,
> + .irq_offset = ilog2(INTR_CCS(1)),
> .domain = XE_FW_RENDER,
> .mmio_base = COMPUTE1_RING_BASE,
> },
> @@ -213,6 +238,7 @@ static const struct engine_info engine_infos[] = {
> .name = "ccs2",
> .class = XE_ENGINE_CLASS_COMPUTE,
> .instance = 2,
> + .irq_offset = ilog2(INTR_CCS(2)),
> .domain = XE_FW_RENDER,
> .mmio_base = COMPUTE2_RING_BASE,
> },
> @@ -220,6 +246,7 @@ static const struct engine_info engine_infos[] = {
> .name = "ccs3",
> .class = XE_ENGINE_CLASS_COMPUTE,
> .instance = 3,
> + .irq_offset = ilog2(INTR_CCS(3)),
> .domain = XE_FW_RENDER,
> .mmio_base = COMPUTE3_RING_BASE,
> },
> @@ -398,6 +425,7 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> hwe->class = info->class;
> hwe->instance = info->instance;
> hwe->mmio_base = info->mmio_base;
> + hwe->irq_offset = info->irq_offset;
> hwe->domain = info->domain;
> hwe->name = info->name;
> hwe->fence_irq = >->fence_irq[info->class];
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> index 39908dec042a..dfeaaac08b7f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> @@ -116,6 +116,8 @@ struct xe_hw_engine {
> u16 instance;
> /** @logical_instance: logical instance of this hw engine */
> u16 logical_instance;
> + /** @irq_offset: IRQ offset of this hw engine */
> + u16 irq_offset;
> /** @mmio_base: MMIO base address of this hw engine*/
> u32 mmio_base;
> /**
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
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