[PATCH 4/8] drm/xe: Move engine base offsets to engine register header

[Lucas De Marchi]

On Thu, Dec 14, 2023 at 10:47:04AM -0800, Matt Roper wrote:
>These offsets are primarily used as parameters for the engine register
>definitions, so it makes more sense to define them in the engine header
>rather than the general register header.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 33 ++++++++++++++++++++++++
> drivers/gpu/drm/xe/regs/xe_regs.h        | 28 --------------------
> 2 files changed, 33 insertions(+), 28 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>index 7f82bef3a0db..5592774fc690 100644
>--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>@@ -10,6 +10,39 @@
>
> #include "regs/xe_reg_defs.h"
>
>+/*
>+ * These *_BASE values represent the MMIO offset where each hardware engine's
>+ * registers start.  The other definitions in this header are parameterized
>+ * macros that will take one of these values as a parameter.
>+ */
>+#define RENDER_RING_BASE			0x02000
>+#define BSD_RING_BASE				0x1c0000
>+#define BSD2_RING_BASE				0x1c4000
>+#define BSD3_RING_BASE				0x1d0000
>+#define BSD4_RING_BASE				0x1d4000
>+#define XEHP_BSD5_RING_BASE			0x1e0000
>+#define XEHP_BSD6_RING_BASE			0x1e4000
>+#define XEHP_BSD7_RING_BASE			0x1f0000
>+#define XEHP_BSD8_RING_BASE			0x1f4000
>+#define VEBOX_RING_BASE				0x1c8000
>+#define VEBOX2_RING_BASE			0x1d8000
>+#define XEHP_VEBOX3_RING_BASE			0x1e8000
>+#define XEHP_VEBOX4_RING_BASE			0x1f8000
>+#define COMPUTE0_RING_BASE			0x1a000
>+#define COMPUTE1_RING_BASE			0x1c000
>+#define COMPUTE2_RING_BASE			0x1e000
>+#define COMPUTE3_RING_BASE			0x26000
>+#define BLT_RING_BASE				0x22000
>+#define XEHPC_BCS1_RING_BASE			0x3e0000
>+#define XEHPC_BCS2_RING_BASE			0x3e2000
>+#define XEHPC_BCS3_RING_BASE			0x3e4000
>+#define XEHPC_BCS4_RING_BASE			0x3e6000
>+#define XEHPC_BCS5_RING_BASE			0x3e8000
>+#define XEHPC_BCS6_RING_BASE			0x3ea000
>+#define XEHPC_BCS7_RING_BASE			0x3ec000
>+#define XEHPC_BCS8_RING_BASE			0x3ee000
>+#define GSCCS_RING_BASE				0x11a000
>+
> #define RING_TAIL(base)				XE_REG((base) + 0x30)
>
> #define RING_HEAD(base)				XE_REG((base) + 0x34)
>diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
>index 4b427ec8cbff..b7d3b42ec003 100644
>--- a/drivers/gpu/drm/xe/regs/xe_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
>@@ -7,38 +7,10 @@
>
> #include "regs/xe_reg_defs.h"
>
>-#define RENDER_RING_BASE			0x02000
>-#define BSD_RING_BASE				0x1c0000
>-#define BSD2_RING_BASE				0x1c4000
>-#define BSD3_RING_BASE				0x1d0000
>-#define BSD4_RING_BASE				0x1d4000
>-#define XEHP_BSD5_RING_BASE			0x1e0000
>-#define XEHP_BSD6_RING_BASE			0x1e4000
>-#define XEHP_BSD7_RING_BASE			0x1f0000
>-#define XEHP_BSD8_RING_BASE			0x1f4000
>-#define VEBOX_RING_BASE				0x1c8000
>-#define VEBOX2_RING_BASE			0x1d8000
>-#define XEHP_VEBOX3_RING_BASE			0x1e8000
>-#define XEHP_VEBOX4_RING_BASE			0x1f8000
>-#define COMPUTE0_RING_BASE			0x1a000
>-#define COMPUTE1_RING_BASE			0x1c000
>-#define COMPUTE2_RING_BASE			0x1e000
>-#define COMPUTE3_RING_BASE			0x26000
>-#define BLT_RING_BASE				0x22000
>-#define XEHPC_BCS1_RING_BASE			0x3e0000
>-#define XEHPC_BCS2_RING_BASE			0x3e2000
>-#define XEHPC_BCS3_RING_BASE			0x3e4000
>-#define XEHPC_BCS4_RING_BASE			0x3e6000
>-#define XEHPC_BCS5_RING_BASE			0x3e8000
>-#define XEHPC_BCS6_RING_BASE			0x3ea000
>-#define XEHPC_BCS7_RING_BASE			0x3ec000
>-#define XEHPC_BCS8_RING_BASE			0x3ee000
>-
> #define DG1_GSC_HECI2_BASE			0x00259000
> #define PVC_GSC_HECI2_BASE			0x00285000
> #define DG2_GSC_HECI2_BASE			0x00374000
>
>-#define GSCCS_RING_BASE				0x11a000
> #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
> #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
> #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)

humn... these bit definitions seem misplaced, but it's unrelated to this
patch, so:


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>-- 
>2.43.0
>