[PATCH] drm/xe/dg2: Drop pre-production workarounds
Gustavo Sousa
gustavo.sousa at intel.com
Fri Dec 15 20:05:15 UTC 2023
Quoting Matt Roper (2023-12-14 18:52:00-03:00)
>Pre-production hardware is anything before C0 (for DG2-G10), before B1
>(for DG2-G11), or before A1 (for DG2-G12). Workarounds specific to such
>hardware was already removed from i915 in commit eaeb4b361452
>("drm/i915/dg2: Drop pre-production GT workarounds") and there's even
>less value keeping these around in the Xe driver.
I did a bit of scripting and also found those (potentially) remaining
ones:
DG2-G10:
14011441408
This one is applied in xe_mocs.c.
14010648519
14010198302
1608949956
These ones seem not to be valid lineage numbers though and, in
the code, we seem to be applying them to any DG2 variant and any
stepping. Thus I'm not really sure here, but thought of sharing
for completeness.
Looking at the details of the records, I see that they apply to
DG2-G10 in the range [a0..b0).
DG2-G11:
16011620976
The implementation matches 22015475538, which is a permanent
workaround for DG2-G11, so I believe we can just remove the
mention of 16011620976 from the code.
--
Gustavo Sousa
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/xe_guc.c | 8 +-
> drivers/gpu/drm/xe/xe_wa.c | 163 -----------------------------
> drivers/gpu/drm/xe/xe_wa_oob.rules | 7 +-
> 3 files changed, 2 insertions(+), 176 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>index 482cb0df9f15..76b31d542e1a 100644
>--- a/drivers/gpu/drm/xe/xe_guc.c
>+++ b/drivers/gpu/drm/xe/xe_guc.c
>@@ -133,13 +133,10 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
> if (XE_WA(gt, 22012773006))
> flags |= GUC_WA_POLLCS;
>
>- if (XE_WA(gt, 16011759253))
>- flags |= GUC_WA_GAM_CREDITS;
>-
> if (XE_WA(gt, 14014475959))
> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>
>- if (XE_WA(gt, 22011391025) || XE_WA(gt, 14012197797))
>+ if (XE_WA(gt, 22011391025))
> flags |= GUC_WA_DUAL_QUEUE;
>
> /*
>@@ -150,9 +147,6 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
> if (GRAPHICS_VERx100(xe) < 1270)
> flags |= GUC_WA_PRE_PARSER;
>
>- if (XE_WA(gt, 16011777198))
>- flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
>-
> if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))
> flags |= GUC_WA_CONTEXT_ISOLATION;
>
>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>index 23f1285135b8..4b3fa1a5a3e6 100644
>--- a/drivers/gpu/drm/xe/xe_wa.c
>+++ b/drivers/gpu/drm/xe/xe_wa.c
>@@ -125,13 +125,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>
> /* DG2 */
>
>- { XE_RTP_NAME("16010515920"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10),
>- GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(VIDEO_DECODE)),
>- XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),
>- XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>- },
> { XE_RTP_NAME("22010523718"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
> XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
>@@ -140,61 +133,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
> XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
> XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
> },
>- { XE_RTP_NAME("14012362059"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
>- },
>- { XE_RTP_NAME("14012362059"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
>- },
>- { XE_RTP_NAME("14010948348"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14011037102"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14011371254"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14011431319"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(UNSLCGCTL9440,
>- GAMTLBOACS_CLKGATE_DIS |
>- GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
>- GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
>- GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
>- GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
>- GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
>- GAMTLBBLT_CLKGATE_DIS),
>- SET(UNSLCGCTL9444,
>- GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
>- GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
>- GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
>- GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
>- GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
>- GAMTLBMERT_CLKGATE_DIS |
>- GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
>- GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14010569222"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14011028019"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
>- },
>- { XE_RTP_NAME("14010680813"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_GAMSTLB_CTRL,
>- CONTROL_BLOCK_CLKGATE_DIS |
>- EGRESS_BLOCK_CLKGATE_DIS |
>- TAG_BLOCK_CLKGATE_DIS))
>- },
> { XE_RTP_NAME("14014830051"),
> XE_RTP_RULES(PLATFORM(DG2)),
> XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
>@@ -375,13 +313,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
> POLYGON_TRIFAN_LINELOOP_DISABLE))
> },
>- { XE_RTP_NAME("22012826095, 22013059131"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
>- FUNC(xe_rtp_match_first_render_or_compute)),
>- XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
>- MAXREQS_PER_BANK,
>- REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
>- },
> { XE_RTP_NAME("22012826095, 22013059131"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11),
> FUNC(xe_rtp_match_first_render_or_compute)),
>@@ -389,28 +320,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> MAXREQS_PER_BANK,
> REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
> },
>- { XE_RTP_NAME("22013059131"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
>- FUNC(xe_rtp_match_first_render_or_compute)),
>- XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
>- },
> { XE_RTP_NAME("22013059131"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11),
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
> },
>- { XE_RTP_NAME("14010918519"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
>- FUNC(xe_rtp_match_first_render_or_compute)),
>- XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
>- FORCE_SLM_FENCE_SCOPE_TO_TILE |
>- FORCE_UGM_FENCE_SCOPE_TO_TILE,
>- /*
>- * Ignore read back as it always returns 0 in these
>- * steps
>- */
>- .read_mask = 0))
>- },
> { XE_RTP_NAME("14015227452"),
> XE_RTP_RULES(PLATFORM(DG2),
> FUNC(xe_rtp_match_first_render_or_compute)),
>@@ -432,16 +346,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
> },
>- { XE_RTP_NAME("22012654132"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
>- FUNC(xe_rtp_match_first_render_or_compute)),
>- XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
>- /*
>- * Register can't be read back for verification on
>- * DG2 due to Wa_14012342262
>- */
>- .read_mask = 0))
>- },
> { XE_RTP_NAME("22012654132"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11),
> FUNC(xe_rtp_match_first_render_or_compute)),
>@@ -460,30 +364,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
> },
>- { XE_RTP_NAME("14013392000"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))
>- },
>- { XE_RTP_NAME("14012419201"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
>- DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
>- },
>- { XE_RTP_NAME("14012419201"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
>- DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
>- },
>- { XE_RTP_NAME("1308578152"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
>- ENGINE_CLASS(RENDER),
>- FUNC(xe_rtp_match_first_gslice_fused_off)),
>- XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1,
>- REPLAY_MODE_GRANULARITY))
>- },
> { XE_RTP_NAME("22010960976, 14013347512"),
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
>@@ -494,34 +374,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> XE_RTP_ACTIONS(SET(ROW_CHICKEN,
> MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))
> },
>- { XE_RTP_NAME("22010430635"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
>- DISABLE_GRF_CLEAR))
>- },
>- { XE_RTP_NAME("14013202645"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
>- },
>- { XE_RTP_NAME("14013202645"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
>- },
>- { XE_RTP_NAME("22012532006"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
>- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
>- },
>- { XE_RTP_NAME("22012532006"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
>- ENGINE_CLASS(RENDER)),
>- XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
>- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
>- },
> { XE_RTP_NAME("14015150844"),
> XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
>@@ -650,21 +502,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>
> /* DG2 */
>
>- { XE_RTP_NAME("16011186671"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),
>- SET(VFLSKPD, DIS_OVER_FETCH_CACHE))
>- },
>- { XE_RTP_NAME("14010469329"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
>- XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))
>- },
>- { XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
>- XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
>- XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
>- DISABLE_CPS_AWARE_COLOR_PIPE))
>- },
> { XE_RTP_NAME("16013271637"),
> XE_RTP_RULES(PLATFORM(DG2)),
> XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
>diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
>index 727bdc429212..e73b84e01ea1 100644
>--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>@@ -1,13 +1,8 @@
> 22012773006 GRAPHICS_VERSION_RANGE(1200, 1250)
>-16011759253 SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)
> 14014475959 GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
> PLATFORM(DG2)
> 22011391025 PLATFORM(DG2)
>-14012197797 PLATFORM(DG2), GRAPHICS_STEP(A0, B0)
>-16011777198 SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)
>- SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)
>-22012727170 SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)
>- SUBPLATFORM(DG2, G11)
>+22012727170 SUBPLATFORM(DG2, G11)
> 22012727685 SUBPLATFORM(DG2, G11)
> 16015675438 PLATFORM(PVC)
> SUBPLATFORM(DG2, G10)
>--
>2.43.0
>
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