[PATCH v2 06/10] drm/xe: Add XE_BO_NEEDS_UC flag to force UC mode instead WB

[Matt Roper]

On Thu, Dec 14, 2023 at 07:59:51PM +0100, Michal Wajdeczko wrote:
> When we map BO in GGTT, then by default we are using PAT index
> that corresponds to XE_CACHE_WB but ppcoming feature will require
> use of the PAT index of the XE_CACHE_UC.  Define new BO flag that
> could be used during BO creation to force alternate caching.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_bo.h   | 1 +
>  drivers/gpu/drm/xe/xe_ggtt.c | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> index 9b1279aca127..97b32528c600 100644
> --- a/drivers/gpu/drm/xe/xe_bo.h
> +++ b/drivers/gpu/drm/xe/xe_bo.h
> @@ -44,6 +44,7 @@
>  #define XE_BO_FIXED_PLACEMENT_BIT	BIT(11)
>  #define XE_BO_PAGETABLE			BIT(12)
>  #define XE_BO_NEEDS_CPU_ACCESS		BIT(13)
> +#define XE_BO_NEEDS_UC			BIT(14)
>  /* this one is trigger internally only */
>  #define XE_BO_INTERNAL_TEST		BIT(30)
>  #define XE_BO_INTERNAL_64K		BIT(31)
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 374ae4289fa0..c239782498a7 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -335,7 +335,8 @@ int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,
>  
>  void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
>  {
> -	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
> +	u16 cache_mode = bo->flags & XE_BO_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB;
> +	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode];
>  	u64 start = bo->ggtt_node.start;
>  	u64 offset, pte;
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation