[PATCH 2/3] drm/xe: Rename num_slices to num_cslices

[Niranjana Vishwanathapura]

'cslice' indicates compute slice and removes any
ambiguity with 'gslice' used elsewhere in the driver.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
---
 drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
index ee1065c44da7f..173b119a21c00 100644
--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
@@ -21,10 +21,10 @@
 /* Get CCS mode mask to disable all compute slices */
 static u32 xe_gt_ccs_mode_disabled(struct xe_gt *gt)
 {
-	int i, num_slices = hweight32(gt->info.__engine_mask & XE_HW_ENGINE_CCS_MASK);
+	int i, num_cslices = hweight32(gt->info.__engine_mask & XE_HW_ENGINE_CCS_MASK);
 	u32 mode = 0;
 
-	for (i = 0; i < num_slices; i++)
+	for (i = 0; i < num_cslices; i++)
 		mode |= CCS_MODE_CSLICE(i, CCS_MODE_CSLICE_ASSIGNMENT);
 
 	return mode;
@@ -33,7 +33,7 @@ static u32 xe_gt_ccs_mode_disabled(struct xe_gt *gt)
 void xe_gt_ccs_mode_apply(struct xe_gt *gt)
 {
 	u32 mode = xe_gt_ccs_mode_disabled(gt); /* disable all by default */
-	int num_slices = hweight32(CCS_MASK(gt));
+	int num_cslices = hweight32(CCS_MASK(gt));
 	struct xe_device *xe = gt_to_xe(gt);
 	u32 num_engines = gt->ccs_mode;
 	int width, cslice = 0;
@@ -43,8 +43,8 @@ void xe_gt_ccs_mode_apply(struct xe_gt *gt)
 		return;
 
 	xe_assert(xe, xe_gt_ccs_mode_enabled(gt));
-	xe_assert(xe, num_engines <= num_slices);
-	xe_assert(xe, !(num_slices % num_engines));
+	xe_assert(xe, num_engines <= num_cslices);
+	xe_assert(xe, !(num_cslices % num_engines));
 
 	/*
 	 * Loop over all available slices and assign each a user engine.
@@ -64,7 +64,7 @@ void xe_gt_ccs_mode_apply(struct xe_gt *gt)
 	 *   slice 2: ccs2
 	 *   slice 3: ccs3
 	 */
-	for (width = num_slices / num_engines; width; width--) {
+	for (width = num_cslices / num_engines; width; width--) {
 		struct xe_hw_engine *hwe;
 		enum xe_hw_engine_id id;
 
@@ -89,8 +89,8 @@ void xe_gt_ccs_mode_apply(struct xe_gt *gt)
 
 	xe_mmio_write32(gt, CCS_MODE, mode);
 
-	xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
-		   mode, config, num_engines, num_slices);
+	xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_cslices:%d\n",
+		   mode, config, num_engines, num_cslices);
 }
 
 static ssize_t
@@ -119,7 +119,7 @@ ccs_mode_store(struct device *kdev, struct device_attribute *attr,
 {
 	struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
 	struct xe_device *xe = gt_to_xe(gt);
-	u32 num_engines, num_slices;
+	u32 num_engines, num_cslices;
 	int ret;
 
 	ret = kstrtou32(buff, 0, &num_engines);
@@ -130,10 +130,10 @@ ccs_mode_store(struct device *kdev, struct device_attribute *attr,
 	 * Ensure number of engines specified is valid and there is an
 	 * exact multiple of engines for slices.
 	 */
-	num_slices = hweight32(CCS_MASK(gt));
-	if (!num_engines || num_engines > num_slices || num_slices % num_engines) {
+	num_cslices = hweight32(CCS_MASK(gt));
+	if (!num_engines || num_engines > num_cslices || num_cslices % num_engines) {
 		xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n",
-			  num_engines, num_slices);
+			  num_engines, num_cslices);
 		return -EINVAL;
 	}
 
-- 
2.43.0