[Intel-xe] [PATCH] drm/xe: Do not spread i915_reg_defs.h include
Matt Roper
matthew.d.roper at intel.com
Mon Feb 27 15:53:06 UTC 2023
On Sat, Feb 25, 2023 at 12:10:39PM -0800, Lucas De Marchi wrote:
> Reduce the use of i915_reg_defs.h so it can be encapsulated in a single
> place.
>
> 1) If it was being included by mistake, remove
> 2) If it was included for FIELD_GET()/FIELD_PREP()/GENMASK() and the
> like, just include <linux/bitfield.h>
> 3) If it was included to be able to define additional registers, move
> the registers to the relavant headers (regs/xe_regs.h or
> regs/xe_gt_regs.h)
>
> v2:
> - Squash commit fixing i915_reg_defs.h include and with the one
> introducing regs/xe_reg_defs.h
> - Remove more cases of i915_reg_defs.h being used when all it was
> needed was linux/bitfield.h (Matt Roper)
> - Move some registers to the corresponding regs/*.h file (Matt Roper)
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>
> This is the leftover change from
> https://lore.kernel.org/intel-xe/20230225001548.1743820-1-lucas.demarchi@intel.com
> The resst has been applied.
>
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 +++++++-
> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 11 +++++++++++
> drivers/gpu/drm/xe/regs/xe_regs.h | 4 +++-
> drivers/gpu/drm/xe/xe_device.c | 3 +--
> drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
> drivers/gpu/drm/xe/xe_gt_pagefault.c | 1 +
> drivers/gpu/drm/xe/xe_gt_topology.c | 15 +++++----------
> drivers/gpu/drm/xe/xe_guc.c | 8 --------
> drivers/gpu/drm/xe/xe_guc_reg.h | 6 +++++-
> drivers/gpu/drm/xe/xe_migrate.c | 1 +
> drivers/gpu/drm/xe/xe_pcode_api.h | 2 ++
> drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 --
> drivers/gpu/drm/xe/xe_rtp.h | 2 --
> drivers/gpu/drm/xe/xe_rtp_types.h | 2 --
> drivers/gpu/drm/xe/xe_step.c | 2 ++
> 16 files changed, 40 insertions(+), 31 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_reg_defs.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 6dfa3cf2fd43..2aa67d001c34 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -8,7 +8,7 @@
>
> #include <asm/page.h>
>
> -#include "i915_reg_defs.h"
> +#include "regs/xe_reg_defs.h"
>
> #define RING_TAIL(base) _MMIO((base) + 0x30)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 9290505d6596..4d0f09cd447c 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -6,7 +6,7 @@
> #ifndef _XE_GT_REGS_H_
> #define _XE_GT_REGS_H_
>
> -#include "i915_reg_defs.h"
> +#include "regs/xe_reg_defs.h"
>
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 _MMIO(0xd00)
> @@ -108,6 +108,12 @@
> #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
> #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
>
> +#define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */
> +#define XELP_EU_MASK REG_GENMASK(7, 0)
> +#define XELP_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
> +#define XEHP_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
> +#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
> +
> #define GEN6_GDRST _MMIO(0x941c)
> #define GEN11_GRDOM_GUC REG_BIT(3)
> #define GEN6_GRDOM_FULL (1 << 0)
> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> new file mode 100644
> index 000000000000..5f6735697d9c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_REG_DEFS_H_
> +#define _XE_REG_DEFS_H_
> +
> +#include "../../i915/i915_reg_defs.h"
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index a697162e1a77..2e7fbdedb5eb 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -5,7 +5,7 @@
> #ifndef _XE_REGS_H_
> #define _XE_REGS_H_
>
> -#include "i915_reg_defs.h"
> +#include "regs/xe_reg_defs.h"
>
> #define GU_CNTL _MMIO(0x101010)
> #define LMEM_INIT REG_BIT(7)
> @@ -70,6 +70,8 @@
> #define PIPE_DSI0_OFFSET 0x7b000
> #define PIPE_DSI1_OFFSET 0x7b800
>
> +#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084)
> +
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> #define GEN8_PCU_IIR _MMIO(0x444e8)
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 45e3c740fda2..4eb6786b11f0 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -12,6 +12,7 @@
> #include <drm/drm_managed.h>
> #include <drm/xe_drm.h>
>
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_debugfs.h"
> #include "xe_display.h"
> @@ -405,8 +406,6 @@ static void device_kill_persitent_engines(struct xe_device *xe,
> mutex_unlock(&xe->persitent_engines.lock);
> }
>
> -#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4F084)
> -
> void xe_device_wmb(struct xe_device *xe)
> {
> struct xe_gt *gt = xe_device_get_gt(xe, 0);
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
> index c31987d2177c..2a6cd38c8cb7 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
> @@ -6,7 +6,7 @@
> #ifndef _XE_GT_MCR_H_
> #define _XE_GT_MCR_H_
>
> -#include "i915_reg_defs.h"
> +#include "regs/xe_reg_defs.h"
>
> struct drm_printer;
> struct xe_gt;
> diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
> index 0e7047b89a83..1677640e1075 100644
> --- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
> +++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
> @@ -5,6 +5,7 @@
>
> #include "xe_gt_pagefault.h"
>
> +#include <linux/bitfield.h>
> #include <linux/circ_buf.h>
>
> #include <drm/drm_managed.h>
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index c76aaea1887c..2123f84be336 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -7,18 +7,13 @@
>
> #include <linux/bitmap.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt.h"
> #include "xe_mmio.h"
>
> #define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
> #define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)
>
> -#define XELP_EU_ENABLE 0x9134 /* "_DISABLE" on Xe_LP */
> -#define XELP_EU_MASK REG_GENMASK(7, 0)
> -#define XELP_GT_GEOMETRY_DSS_ENABLE 0x913c
> -#define XEHP_GT_COMPUTE_DSS_ENABLE 0x9144
> -#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT 0x9148
> -
> static void
> load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
> {
> @@ -41,7 +36,7 @@ static void
> load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
> {
> struct xe_device *xe = gt_to_xe(gt);
> - u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE);
> + u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg);
> u32 val = 0;
> int i;
>
> @@ -86,10 +81,10 @@ xe_gt_topology_init(struct xe_gt *gt)
> }
>
> load_dss_mask(gt, gt->fuse_topo.g_dss_mask, num_geometry_regs,
> - XELP_GT_GEOMETRY_DSS_ENABLE);
> + XELP_GT_GEOMETRY_DSS_ENABLE.reg);
> load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
> - XEHP_GT_COMPUTE_DSS_ENABLE,
> - XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
> + XEHP_GT_COMPUTE_DSS_ENABLE.reg,
> + XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg);
> load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
>
> xe_gt_topology_dump(gt, &p);
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 661effa9830f..58b9841616e4 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -22,14 +22,6 @@
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
> -#include "i915_reg_defs.h"
> -
> -/* TODO: move to common file */
> -#define GUC_PVC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
> -#define PVC_MOCS_UC_INDEX 1
> -#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(GUC_PVC_MOCS_INDEX_MASK,\
> - index)
> -
> static struct xe_gt *
> guc_to_gt(struct xe_guc *guc)
> {
> diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
> index 513a7e0c8a5a..efd60c186bbc 100644
> --- a/drivers/gpu/drm/xe/xe_guc_reg.h
> +++ b/drivers/gpu/drm/xe/xe_guc_reg.h
> @@ -9,7 +9,7 @@
> #include <linux/compiler.h>
> #include <linux/types.h>
>
> -#include "i915_reg_defs.h"
> +#include "regs/xe_reg_defs.h"
>
> /* Definitions of GuC H/W registers, bits, etc */
>
> @@ -93,6 +93,10 @@
> #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
> #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
> #define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
> +#define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
> +#define PVC_MOCS_UC_INDEX 1
> +#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK,\
> + index)
>
> #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
> #define GUC_SEND_TRIGGER (1<<0)
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 6c0033cb238f..bc69ec17d5ad 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -5,6 +5,7 @@
>
> #include "xe_migrate.h"
>
> +#include <linux/bitfield.h>
> #include <linux/sizes.h>
>
> #include <drm/drm_managed.h>
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 0762c8a912c7..4e689cd4b23b 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -5,6 +5,8 @@
>
> /* Internal to xe_pcode */
>
> +#include "regs/xe_reg_defs.h"
> +
> #define PCODE_MAILBOX _MMIO(0x138124)
> #define PCODE_READY REG_BIT(31)
> #define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> index b234a8673e54..0e6d542ff1b4 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
> +++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> @@ -9,8 +9,6 @@
> #include <linux/types.h>
> #include <linux/xarray.h>
>
> -#include "i915_reg_defs.h"
> -
> struct xe_reg_sr_entry {
> u32 clr_bits;
> u32 set_bits;
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index d6ba0b7e5042..bd44fd8bbe05 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -11,8 +11,6 @@
>
> #include "xe_rtp_types.h"
>
> -#include "i915_reg_defs.h"
> -
> /*
> * Register table poke infrastructure
> */
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index fac0bd6d5b1e..e87f1b280d96 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -8,8 +8,6 @@
>
> #include <linux/types.h>
>
> -#include "i915_reg_defs.h"
> -
> struct xe_hw_engine;
> struct xe_gt;
>
> diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
> index ca77d0971529..14f482f29ae4 100644
> --- a/drivers/gpu/drm/xe/xe_step.c
> +++ b/drivers/gpu/drm/xe/xe_step.c
> @@ -5,6 +5,8 @@
>
> #include "xe_step.h"
>
> +#include <linux/bitfield.h>
> +
> #include "xe_device.h"
> #include "xe_platform_types.h"
>
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
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