[Intel-xe] [PATCH] drm/xe: Add fake workaround to maintain backward compatible in MI_BATCH_BUFFER_START

[José Roberto de Souza]

i915 has the same fake workaround to return MI_BATCH_BUFFER_START
nested batch buffer behavior in DG2 and newer platforms to the same
behavior as older platforms.

So here cleaning up TGL_NESTED_BB_EN in MI_MODE to disable third level
chained batch buffer level.

Bspec: 45974, 45718
Cc: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/xe/xe_rtp_types.h |  2 ++
 drivers/gpu/drm/xe/xe_wa.c        | 11 +++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 14e5d4dbb4c15..72f3e2e83014f 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -52,6 +52,8 @@ enum {
 	XE_RTP_MATCH_FUNC,
 };
 
+#define IP_VERSION_FOREVER 9900
+
 /** struct xe_rtp_rule - match rule for processing entry */
 struct xe_rtp_rule {
 	u8 match_type;
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 3325de3edf691..3616b2284d186 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -285,6 +285,17 @@ static const struct xe_rtp_entry lrc_was[] = {
 		     DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
 		     XE_RTP_FLAG(MASKED_REG))
 	},
+	{ XE_RTP_NAME("FakeWaDisableNestedBBMode"),
+	  /*
+	   * This is a "fake" workaround defined by software to ensure we
+	   * maintain reliable, backward-compatible behavior for userspace with
+	   * regards to how nested MI_BATCH_BUFFER_START commands are handled.
+	   */
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, IP_VERSION_FOREVER)),
+	  XE_RTP_CLR(RING_MI_MODE(0),
+		     TGL_NESTED_BB_EN,
+		     XE_RTP_FLAG(MASKED_REG, ENGINE_BASE))
+	},
 	{}
 };
 
-- 
2.39.1