[Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface

Dixit, Ashutosh ashutosh.dixit at intel.com
Sun Jul 9 00:32:21 UTC 2023


On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote:
> On 07-07-2023 07:48, Dixit, Ashutosh wrote:
> > On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote:
> > Also, could you please explain where the requirement to expose these OAG
> > group busy/free registers via the PMU is coming from? Since these are OA
> > registers presumably they can be collected using the OA subsystem.
>
> L0 sysman needs this
> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t
> and xpumanager uses this
> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp

Also there is the above mentioned open regarding this: "Since these are OA
registers presumably they can be collected using the OA subsystem". L0 now
seems to be supporting OA and we are going to provide an OA subsystem for
xe. This probably also needs arch input.


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