[Intel-xe] [RFC] drm/xe/pvc: Force even num engines to use 64B

[Niranjana Vishwanathapura]

On Tue, Jul 11, 2023 at 04:48:32PM +0000, Matthew Brost wrote:
>On Fri, Jun 23, 2023 at 06:41:37PM -0700, Niranjana Vishwanathapura wrote:
>> Wa_16017236439 requires that we update BCS_SWCTRL
>> (via indirect context batch buffer) to set 64B
>> transfers when running on an even-numbered BCS
>> engine and 256B on an odd-numbered BCS engine.
>>
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
>
>Can you include the include a version of thia patch in the series?
>https://patchwork.freedesktop.org/patch/528460/?series=115575&rev=2
>
>IMO it makes sense to merge both of these at the same time.
>

Ok, will do.

Niranjana

>Matt
>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 3 +++
>>  drivers/gpu/drm/xe/xe_wa.c               | 8 +++++++-
>>  2 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> index 79873bf64e8d..af3cfc696692 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> @@ -59,6 +59,9 @@
>>  #define RING_BBADDR(base)			XE_REG((base) + 0x140)
>>  #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
>>
>> +#define BCS_ENGINE_SWCTL(base)			XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
>> +#define BCS_ENGINE_SWCTL_DISABLE_256B		REG_BIT(2)
>> +
>>  /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
>>  #define BLIT_CCTL(base)				XE_REG((base) + 0x204)
>>  #define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 5eaa9bed9d12..341877acf05d 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -518,6 +518,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>>  		       GRAPHICS_STEP(B0, C0)),
>>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
>>  	},
>> +	{ XE_RTP_NAME("16017236439"),
>> +	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
>> +		       FUNC(xe_rtp_match_even_instance)),
>> +	  XE_RTP_ACTIONS(SET(BCS_ENGINE_SWCTL(0),
>> +			     BCS_ENGINE_SWCTL_DISABLE_256B,
>> +			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),
>> +	},
>>
>>  	/* Xe_LPG */
>>  	{ XE_RTP_NAME("14017856879"),
>> @@ -525,7 +532,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>>  	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
>>  	},
>> -
>>  	{}
>>  };
>>
>> --
>> 2.21.0.rc0.32.g243a4c7e27
>>